Vitesse offers third-generation 160Gb/s intelligent switch fabric, OC-48 traffic management and SAR
Sept. 13, 2001--Vitesse Semiconductor Corporation released details for its third-generation Intelligent Switch Fabric. The company also announced general sampling of its pin-compatible successor to its OC-48 Traffic Management and SAR engine.
Vitesse Semiconductor Corporation (NASDAQ:VTSS) released technical details for its third generation Intelligent Switch Fabric, the TeraStream chipset. TeraStream serves the high-end metro and core equipment markets.
This feature-rich chipset supports OC-48 and OC-192 port speeds with a maximum aggregate user bandwidth of 160Gb/s. TeraStream is the newest member of Vitesse's switch fabric platform, joining the GigaStream and CrossStream products.
This highly integrated chipset incorporates fabric functionality into two components, the VSC871 Queuing Engine on the line card, and the VSC881 Packet Exchange Matrix on the switch card, providing a high level of integration for designers of switches and routers. The Queuing Engine device communicates entirely in-band with the Package Exchange Matrix device via integrated SerDes, which eliminates the need for any additional components and simplifies system design.
TeraStream provides fabric functionality including queuing, scheduling, SerDes, backplane communication, full redundancy, and optimized switching in only two ICs. A fully redundant 160Gb/s system only requires 24 TeraStream chips, 16 on the line cards and 4 per switch card, versus a typical switch fabric implementation of more than 200 chips. With a low component count implementation, Vitesse's TeraStream product provides the lowest overall power and cost solution.
TeraStream's Queuing Engine offers queuing granularity with separate unicast and multicast support, each with 16 classes of traffic, as well as virtual output queues to eliminate head-of-line blocking. The unique integrated queuing structure in TeraStream's Packet Exchange Matrix buffers the ingress traffic and executes multicast replication to relieve congestion and provide more efficient ingress bandwidth utilization across the backplane.
For design flexibility, TeraStream can be configured for up to 16 ports of OC-192 data or 64 ports of OC-48 data or any combination of both up to a maximum of 160Gb/s of aggregate user bandwidth. There is an additional 2x speedup in the backplane. In addition to the active backplane communication, the Queuing Engine employs integrated redundant SerDes to support a 1+1 redundancy scheme with the addition of a single switch card. This redundancy scheme offers end-to-end error protection and a mechanism for maintaining resources during faulty conditions, ensuring zero loss of traffic and continuous operation.
The Queuing Engine has a CSIX interface that supports both OC-48 and OC-192 traffic, increasing the designer's ability to interface with Vitesse's or any CSIX-compatible, third party traffic manager or network processor. Using the CSIX standard interface increases design flexibility and promotes interoperability with best-of-breed components.
TeraStream will be available in production quantities in December, 2001.
The VSC871 Queuing Engine is packaged in a 784-pin BGA, and the VSC881 Packet Exchange Matrix is offered in a 520-pin BGA package.
The company also announced general sampling of the PaceMaker 2.5, the pin-compatible successor to the PaceMaker 2.4 OC-48 Traffic Management and SAR engine available since 1Q'01.
As with the PaceMaker 2.4, the pin-compatible PaceMaker 2.5 allows for simultaneous independent control of up to 256k traffic flows. Traffic policing, scheduling and shaping are provided to allow equipment and network designers to balance congestion control with quality of service and class of service (CoS) constraints for a variety of access, metro and core network applications. PaceMaker 2.5 adds several new features, including Weighted Random Early Detect (W-RED) and Deficit Round Robin (DRR) scheduling. PaceMaker 2.5 also adds support of per-logical-port backpressure from the switch fabric interface, which maximizes system throughput.
The PaceMaker 2.5 is designed to work in combination with Vitesse framer/mapper devices, switch fabric components, and the Vitesse Monitor 4.8 (VSC2450), an Operations, Administration and Maintenance (OAM) device with protection switching capability. Together, the Vitesse components provide system designers a complete end-to-end chip level solution for next generation Internet infrastructure equipment.
The example line card depicted in the figure highlights how the Vitesse PaceMaker / Monitor combination provides the industry's only two chip solution for OC-48 ATM line card applications. The PaceMaker and Monitor devices have been developed at Vitesse's Research Triangle Park, North Carolina location.
PaceMaker 2.5 interfaces to the outside world via two independent standard UTOPIA3 or POSPHY3 ports and a 32-bit 66Mhz PCI interface for connection to a host CPU. The 756-pin ABGA device is available now and is priced at $1010 in quantities of 1,000.
Vitesse Semiconductor Corporation is a designer and supplier of innovative, high-performance integrated circuits (ICs) and optical modules used in next generation networking and optical communications equipment. For more information, visit www.vitesse.com.