Cortina offers 10G Octal EDC PHY with small footprint

Communications semiconductor vendor Cortina Systems, Inc. has unveiled the CS4342, an octal 10-Gbps electronic dispersion compensation (EDC) PHY. The chip delivers low latency and standards compliance in the smallest footprint available, the company asserts.

The CS4342 PHY supports eight full-duplex 10G links or two full-duplex 40G links. Both transmit and receive paths include clock and data recovery (CDR) circuits. The chip’s operating frequency range supports Gigabit Ethernet; 1G, 2G, 4G, and 8G Fibre Channel; as well as SONET (9.5 - 11.3G) and 10 Gigabit Ethernet.

The PHY complies with 10G SFP+ and 802.3ba 40G and 100G nPPI and nAUI specifications. The transmit path includes a 10Gbase-KR compliant 3 tap transmit pre-emphasis capability. The transmit pre-emphasis, paired with the receive EDC, enables the device to support 10Gbase-KR, 8G Fibre Channel, and telecom backplane applications.

Thus, the chip can support multiple designs for multiple transmission distances. But it’s the CS4342's size and low latency operation that make it stand out, according to Scott Feller, product line director at Cortina. The chip measures 17x17-mm, which is 34% smaller than other octal 10G PHYs, he says. Meanwhile, the device’s analog design means a latency of only about 1 nsec, he says.

The Cortina CS4342 device is currently sampling.

"With the majority of datacenter interconnect bandwidth for the next few years expected to be handled by 10GbE and 40GbE, high density, small footprint 10GbE and 40GbE solutions are critical to handling the exponential growth in bandwidth intensive consumer applications like uploading photos to Facebook, videos to YouTube and streaming high-definition video. Video is expected to be one of the main bandwidth drivers of the Internet in the near future," commented Brad Smith, senior vice president at market research firm LightCounting, via a Cortina press release. "Space is at a premium in these high-density solutions, whether it is switch faceplate or PCB board area, driving the requirement for higher integration and smaller footprint across all components in the system."

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