Active WDM components have relied primarily on complementary metal oxide semiconductor-based integrated circuits. A combination of bipolar and standard CMOS technology on the same substrate can improve performance.
With speeds of communication equipment constantly increasing, the design of the physical layer to support these systems is becoming more complicated. The requirement is not only for speed, but also to meet the right levels of integration, power specifications, and standards compliance.
Within the physical layer for an OC-48/STM-16 optical interface, the optical module does the electrical-to-optical and optical-to-electrical conversions (see Fig. 1). The serializer/deserializer (SERDES) converts a serial stream into a parallel stream, and back again; the framer manages the SONET/SDH overhead and maps data into the payload.
The SERDES device requires a phase-locked loop for clock multiplication, another loop for clock and data recovery, and high-speed logic for multiplexing and demultiplexing functions. The SERDES must exceed the Telcordia jitter specification for the system to be compliant. The most popular technologies for building SERDES devices are gallium arsenide (GaAs), silicon germanium, silicon complementary metal oxide semiconductor (CMOS), and silicon bipolar CMOS (BiCMOS). The technology chosen for building 2.5-Gbit/s and faster SERDES devices plays a significant role in the complexity of the design and the performance of the device.
The design requires transistors that provide high switching speeds and high gain, as well as the use of matched transistors. The switching speed of the circuit is called fmax. It defines the maximum speed the circuit can switch, from a low to high state and vice versa. As a rule of thumb, chip designers require a technology with an fmax five times greater than the speed of the SERDES device.
Transistor gain defines the amount of current amplification of a single transistor. Designers utilize this characteristic to build current sources for use in analog functions, such as voltage-controlled oscillators for use in phase-locked loops. High gain also makes it possible to create high-speed output buffers and low-voltage input buffers.
Speed is not the only issue. SERDES devices must generate very low jitter to meet standards while tolerating large amounts of jitter to be able to recover transmission signals. Chip designers must match data paths inside the chip and isolate high-speed signals to ensure low noise and low jitter. Typically, higher-gain transistors create less jitter or noise in the SERDES device.
Serializer/deserializer devices may require low input sensitivity to be integrated into the optical module. The low input sensitivity allows optical-module components to receive signals directly from a transimpedance amplifier, which removes the requirement for a limiting amplifier.
Because of the high speed and stringent jitter specifications, many SERDES devices have been designed in GaAs. This material has a very high fmax, on the order of 100 GHz, and a high transistor gain, on the order of 100. The combination of high gain and high fmax gives designers the capability to create 2.5-Gbit/s and faster SERDES devices.
Unfortunately, GaAs is an expensive technology compared with CMOS. Gallium arsenide wafers are much smaller when compared with silicon, transistor geometries are much larger, and yield is more difficult to control than CMOS.
ADVANTAGES OF CMOS
Complementary metal oxide semiconductor has been the technology of choice for logic- or memory-intensive designs. CMOS exhibits low power consumption and is capable of integrating high densities of logic and memory. It is efficient for these applications because it only consumes power when the transistors are switching; when the transistors are static they do not consume power. CMOS also scales to smaller geometries.
High-speed SERDES designs require CMOS transistors for analog and mixed-signal functions. In the past, transistor speeds were not fast enough to build high-speed designs. As the geometries for CMOS decrease, fmax increases, enabling designers to increase the frequencies of their chips. However, the output-current gain also decreases with the geometry of the CMOS transistor.
This reduction in gain forces designers to build multistage amplifiers for analog functions. Because CMOS requires more transistors to build multistage amplifiers that create high current gain, noise becomes a difficult problem for chip designers to overcome.
Input sensitivity in CMOS also becomes more challenging with increasing speed. Transistor gain and transistor matching influence input sensitivity. The voltage threshold for CMOS transistors is specified as Vt. The Vt mismatch for CMOS is on the order of 10 to 20 mV, about ten times greater than for bipolar transistors. The transistor mismatch and the additional transistors required for multistage amplifiers create a difficult problem chip designers.
Finally, at high frequencies CMOS may not deliver the same low-power benefits that are achieved for logic and memory devices because more transistors are required to build multistage drivers to achieve high gain, and as frequencies increase, static time decreases—therefore the transistors consume more power.
Silicon germanium and silicon BiCMOS involve similar processes. They both combine the best of CMOS and bipolar technologies. They allow designers to use bipolar transistors for mixed-signal and analog functions as well as CMOS transistors for slower-speed logic and memory functions. Because silicon germanium BiCMOS provides higher fmax and transistor gain than silicon BiCMOS, it has been applied primarily to the 10-Gbit/s market.
Silicon germanium BiCMOS processes are more expensive to manufacture than CMOS because of the lower-volume production and extra fabrication steps required for both the bipolar transistor and germanium deposition. Typically, silicon BiCMOS processes are also more expensive than CMOS for the same production-volume and fabrication reasons.
Designers facing requirements for a physical-layer device that performs complete parallel-to-serial and serial-to-parallel conversion—including voltage-controlled oscillators for both clock and data recovery and clock synthesis—have begun selecting BiCMOS. The resulting device can be optimized for full SONET/SDH compliance, operating at OC-48/STM16 speeds. It comfortably exceeds the jitter specifications required for SONET/SDH while exhibiting low power consumption and low input sensitivity (see Fig. 2).
For analog and mixed-signal functions, bipolar transistors are used. Bipolar transistors are also used in the voltage-controlled oscillators, where high gain is important to reduce jitter; in the high-speed serial-input buffers, where they are used to increase the sensitivity; and on the output buffers, where they are used to increase drive strength. CMOS transistors are used for logic and memory functions.
This combination of bipolar and CMOS transistors delivers exceptionally low power consumption of 0.8 W for the complete SERDES and clock-and-data-recovery function. Such devices can achieve maximum jitter generation of 0.05 UI (20 ps) peak-to-peak and 0.007 UI (<3 ps) RMS, well below the SONET/SDH requirements of 0.1 UI and 0.01 UI, respectively; the chip has a 50% jitter tolerance margin and easily meets the specification for jitter transfer (see Fig. 3). It also has an exceptionally low input sensitivity of 50 mV, low enough to remove the requirement for a limiting amplifier in most optical systems.
None of this would have been possible using bipolar or CMOS technologies alone, which is why BiCMOS has a significant role to play in the design of high-speed communications integrated circuits.
Michael Bollesen is product-line marketing manager in the communication products division of Cypress Semiconductor, 3901 North First St., San Jose, CA 95134. Contact him at firstname.lastname@example.org or at 408-943-2782.