Cheap as chips —CMOS at 10Gbit/s


Currently, ICs fabricated in expensive gallium arsenide (GaAs) or indium phosphide (InP) III-V compound semiconductor materials are needed to achieve the transistor frequencies for operation at 10 and 40Gbit/s data rates.— with cheaper but electronically slower silicon used for lower data rates.

But over the past few years the introduction of silicon-germanium (SiGe) bipolar transistor technology to mass production has boosted silicon's capabilities to the 10Gbit/s and even 40Gbit/s regimes.

Typically, high-speed devices are made in InP, GaAs or SiGe first, then later migrated to complementary metal-oxide semiconductor (CMOS) silicon transistor technology. CMOS allows for smaller, more highly integrated ICs which cost less and consume less power. Such lower-power components are key to developing higher-port-density board designs to enable equipment to address more applications in confined environments with improved performance and reliability.

For example, good signal performance, jitter margin, power consumption and integration, while lowering cost and power per port and speeding time-to-market, enable the high transmission signal quality needed for multi-service metro edge to core networks.

In previous generations of CMOS, the resulting signals have not been strong enough to stay coherent at high speeds, and signal performance is critical, particularly as the required reach increases.

But in recent years the shrinkage of CMOS dimensions has increased performance such that it can be used in ICs operating at up to 2.5Gbit/s. For example, in May, AMCC launched its S3485 OC-48 2.5Gbit/s transceiver, which uses Taiwanese foundry UMC's 0.13µm CMOS fabrication process.

More recently, the transition from 0.18µm to 0.13µm has enabled CMOS to handle 10Gbit/s and now perhaps 40Gbit/s data rates, bringing the advantages of CMOS to long- and ultra-long-haul SONET/SDH applications. This is particularly applicable for transport physical-layer (PHY) transceiver ICs. These form a multiplexer/demultiplexer combination that resides on a network line-card at the boundary between the physical (fibre) optical layer and the electronic information processing layers. These ICs therefore provide the vital bridge for improved, multi-rate optical performance with multi-protocol support for lower-speed CMOS electronic components such as protocol framers, media access controllers etc.

For OC-192 SONET, on the transmission end, a PHY IC takes 16 streams of 622Mbit/s each and combines them into a single 10Gbit/s signal; on the receiving end, it breaks a 10Gbit/s signal into 622Mbit/s feeds, which are more easily handled by the internal electronic circuitry.

For the above interface scheme, says Vladimir Kozlov, senior analyst for RHK's global optical components service, "the emergence of the OIF's SFI-4.2 compatible ICs will facilitate the adoption of 10Gbit/s small-form-factor transceiver modules such as X2 and XPAK".

RHK's director of optical transport semiconductors, Allan Armstrong, adds that, by 2005, CMOS will surpass other process technologies for OC-192 PHY components due to its "power and integration advantages". More specifically, IDC's Sean Lavey reckons that the 10Gbit/s PHY IC market should grow from USD276m in 2003 to USD780m in 2006.

Such growth should be aided by the PHY mux/demux evolving from two-chip SiGe-based chip-sets, through two-chip CMOS-based chip-sets, to single-chip CMOS-based ICs.

Broadcom already produces the two-chip 0.13µm CMOS X-PHY 10Gbit/s BCM8124/8125 and BCM8128/8129 mux/demux chipsets. Multi-rate capability enables use for 9.953–10.709Gbit/s OC-192 native, 10 Gigabit Ethernet, and OC-192 forward error correction rates in long- and ultra-long-haul applications. Integration of a clock multiplication unit (CMU), clock and data recovery (CDR), limiting amplifier, and features to support requirements for 200- and 300-pin multi-source agreement modules give an average power consumption of just 1.4W and can reduce system size by 30% and power by 50%.

Jitter performance is just 2 milli-unit interval (mUI) RMS (compared to 10mUI RMS allowed by the ITU SONET specification). Broadcom says that the extra jitter margin allows reach to be extended to long-haul by tolerating the associated additional jitter, while also allowing relaxed jitter specification and the use of lower-cost components for short-reach optical components in metro area networks.

"Broadcom's third-generation 10 Gigabit PHY technology sets a new performance standard and clearly marks the transition point for CMOS," said RHK's Armstrong when it was sampled last March.

AMCC already had SiGe first-generation S3091/S3092 and second-generation S3097/S3098 OC-192 transmitter/receiver chip-sets, but last year started volume production of 0.13µm CMOS-based third-generation transceivers that combine low power and high performance in a single-chip device:

  • the 9.953–10.709Gbit/s S19206 for SONET/SDH OC-192 and FEC.
  • the low-cost 9.953–10.3125Gbit/s S19210 for SONET/SDH OC-192 short-reach STS-192 and 10 Gigabit Ethernet.

At SuperComm 2002, AMCC demonstrated the first single-chip, serial, 10Gbit/s SONET PHYs in CMOS. Fabricated in 0.13µm CMOS at Taiwanese foundry UMC, the SuperPHY family of five AnyReach solutions is optimised for multiple-reach systems:

  • S19226 — a low-power (700mW) short-reach OC-192/10GbE transceiver.
  • S19211 — the lowest-power intermediate-reach transceiver (900mW, 35% less than competing solutions). An operating range of 9.9–11.1Gbit/s also made it the first CMOS transceiver for FEC-encoded 10 Gigabit Ethernet (10GbE) data in metro applications.
  • S19215 — the first 10Gbit/s transceiver to support the OIF SFI-4.2 interface, enabling protocol-agnostic hot-pluggable modules including 10GbE, SONET, FEC and G.709 over the same link.
  • S3193 Transmitter/S3094 Receiver, for metro transport and long reach.

AMCC combined SuperPHY with the Niagara (S19208) EFEC mapper for enhanced FEC (EFEC) and dispersion compensation intellectual property in the first generation of its EYEMAX technology (targeted at 10Gbit/s metro transport and long-reach).

AMCC has just sampled the first protocol-agnostic, 10Gbit/s architecture enabling SONET/SDH hot-pluggable smaller-form-factor 70-pin optics modules. This was enabled by the S19215 together with the Columbia 192 (S19218) 10GbE and OC-192 Packet-Over SONET framer/mapper chip, which supports the SFI-4.2 interface.

Agere Systems, meanwhile, had a SiGe-based two-chip PHY, with separate mux and demux chips, but in early 2003 it will sample the single-chip 0.13µm CMOS-based TSCV0110G FlexPHY. To reduce board space and increase performance, flexibility and functionality, the FlexPHY integrates a CMU and 16:1mux/1:16demux. It incorporates a highly sensitive limiting amplifier with programmable amplitude threshold adjustment, as well as a CDR with programmable phase sampling point adjustment. Power consumption is 1W versus most competitive solutions' 1.4–2.0W. This more than doubles the density over two-chip solutions. It also uses multi-rate (9.95–10.71Gbit/s), multi-protocol signal integrity technology, supporting data rates for 10GbE, 10 Gigabit Fibre Channel, SONET/SDH OC-192, OC-192 FEC and G.709 FEC.

Agere claims industry-best jitter generation of 30mUI peak-to-peak, compared with 80mUI for SiGe and 50mUI for typical single-chip CMOS. A typical network system jitter generation budget is typically 100mUI. This allows extra flexibility in design for systems from very short reach (VSR) to ultra-long reach (ULR), including DWDM.

Indeed, as CMOS design rules continue to shrink, more functions are integrated (e.g. PHY plus framers and media access controllers) and performance and power consumption improve, it may be that CMOS can reach even 40Gbit/s data rates.

Last September Intel announced that its planned 90nm CMOS manufacturing process is to be enhanced for communications applications, which will now be the first market sector to be addressed. The new capabilities include the use of high-speed SiGe transistors and mixed-signal circuitry to create "faster, more integrated, less-costly communications chips".

"This integration of computing and communications technologies will enable us to create microchips that are twice as fast, contain 2.5 times more transistors and are substantially less expensive than

anything that exists today," said Sean Maloney, executive VP and general manager of Intel's Communications Group. "The combination of mixed-signal, silicon-germanium and our most advanced CMOS manufacturing process will bring the benefits of Moore's Law [which states that the number of transistors on a chip doubles about every two years] to communications silicon."

The new manufacturing process combines Intel's 90nm logic process with advances in mixed-signal technology that enable analogue and digital functions, which previously resided on multiple chips, to be combined on a single chip. Intel will integrate some critical analogue components directly onto silicon and change how some functions are implemented so that they can be integrated into the logic portion of the chip. By changing the implementation method of analogue functions on digital CMOS transistors, communications chips will benefit from Moore's Law in performance, power, integration and cost.

Intel says that the addition of SiGe not only significantly increases the speed but also reduces the noise of transistors for high-speed communications equipment. These transistors have the speed needed for systems that process data at 50Gbit/s and higher. SiGe and CMOS circuitry on Intel's 90nm process could cut the number of chips and processes used to create an optical subsystem in half.

Intel's 90nm communications manufacturing process shares the basic foundation of the its 90nm logic process. This includes high-performance, low-power digital CMOS transistors using strained silicon technology, seven copper interconnect layers with a new low-k dielectric and 1µm2 SRAM memory cells. In addition to SiGe heterojunction bipolar transistors, new features for communications include high-voltage RF analogue CMOS transistors, precision capacitors and resistors for analogue circuits, and high-Q inductors and varactors.

Intel says that manufacturing all of its 90nm communications chips on 300mm wafers will enable high-volume production and a substantial reduction in manufacturing costs. The first communications chips based on the 90nm process are due for introduction in 2003.

Last November Infineon Technologies' Corporate Research division demonstrated a 2:1mux/1:2demux chip-set using 0.13µm CMOS that achieves a data rate of 40Gbit/s, breaking its February record of 25Gbit/s for CMOS comms ICs.

A rate of 40Gbit/s was previously only possible using either (i) complex and expensive GaAs or InP or (ii) SiGe bipolar transistors. The CMOS result was achieved by optimising both the manufacturing process (packing the integrated components densely) and circuit design (pre-latch configuration, transistor size, operating current per stage, gain peaking due inductive loads and a new type of output signal transmission optimisation).

The chip-set was implemented using current mode logic and a differential 50W I/O. A modified form of this circuit technique, which is used widely in SiGe bipolar technology, has now also been successfully used in CMOS.

Using CMOS will enable high-density monolithic integration of the new high-speed circuits with complex logic, reducing power consumption, increasing manufacturing output and lowering production costs.

In initial tests the mux achieved a data rate of 43Gbit/s and consumed just 66mA of current; the demux 40Gbit/s and 72mA. Both used a 1.5V supply. Details will be presented at February's ISSCC 2003 conference in San Francisco.

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