All present and corrected

Feb. 1, 2003

By Mark Telford

Current metropolitan area networks (MANs) are typically built around 155Mbit/s OC-3, 622Mbit/s OC-12 and 2.5Gbit/s OC-48 SONET/SDH rings. Increasing bandwidth demand from xDSL, broadband cable and next-generation wireless deployment is causing traffic bottlenecks between the overbuilt long-haul and growing enterprise/access networks, so carriers are looking for cost-effective ways to upgrade their metro infrastructure.

The preferred solution is to replace OC-48 line-cards with 10Gbit/s OC-192 line-cards and, where necessary, OC-48 systems with new OC-192 systems, especially as cost falls below 2.5 times the cost of OC-48.

However, a typical incumbent's pre-1995 installed metro fibre is of insufficient quality for the rising reach of unamplified metro network spans (up to 120km) even at 2.5Gbit/s rates, leading to impairments at 10Gbit/s such as optical nonlinearity, chromatic dispersion (CD), polarisation-mode dispersion (PMD), and amplifier-induced four-wave mixing. These degrade signal-to-noise ratio and increase bit-error rate (BER) in digital data during transmission. Compensating for such effects can therefore be necessary, particularly for 40Gbit/s OC-768 rates.

Dispersion compensation is typically optical. However, the limitations of existing technologies require fibre to be dug up to insert bulky and expensive amplifiers — marginally acceptable for long haul but not for metro, preventing widespread adoption of OC-192.

Other direct dispersion compensation techniques, which try to prevent errors, include optical-to-electrical-to-optical regeneration, which is even more expensive, and equalisation dispersion correction in the electrical domain — not yet commercially available.

A complementary technique is the forward error correction of such transmission errors in the electrical domain after they have occurred, retaining signal quality for a better BER in noisy environments.

Used for many years in both digital data storage (against scratches on disks) and transmission (against interference in wireless, satellite, digital TV/DVB, and xDSL modems), FEC does not need much increase in system complexity. FEC can be used either to extend reach between electrical regenerators, to increase the number of DWDM channels by tightening their spacing, or to relax specifications for reduced cost.

Systematic block error correction codes (ECCs) segment payload data into blocks of k consecutive information symbols (bytes) of a consistent size (information word).

Before transmission, in block codes the FEC encoder's mathematical algorithm takes each k-symbol information block, divides it by a generator polynomial and appends a set of r redundant/parity symbols derived from the remainder, forming an n-symbol codeword block (n, k), where n=k+r. The most common codes are "Reed Solomon", RS(n,k), which can be implemented in generic CMOS silicon and form an error-control encoder/decoder (codec).

At the receiver, the decoder first encodes the received information block exactly as the encoder did. If there are no errors, the result yields the same codeword as that received. If there are errors, then the parity and hence codeword generated will be different.

The correct codeword will involve the least possible number of changes to the received word. The decoder operates on the entire codeword, determining which symbols must be changed and the amount of change needed for a valid codeword to be generated. Decoding first uses one parity byte to determine the location of each error and then one parity byte to modify each error symbol. When the "closest valid codeword" is found, all the symbols inserted by the FEC are removed, the payload data is reordered, and the "information word" is output.

Since the channel carries data plus parity in the same time as the information period, the channel data rate must exceed the information data rate. The addition of parity (decreasing the ratio k/n) improves error-correction performance, but requires encoded data output rate (transmission bandwidth) to be an increased by n/k. But for just a small rate overhead, FEC can either keep the BER constant while reducing transmission power or reduce BER without increasing transmission power.

The corresponding improvement in signal-to-noise ratio is the coding gain (see Figure 1), equivalent to the power decrease that would be required to maintain the same BER that otherwise results without the use of FEC coding.

  • In-band BCH-3(4359,4320) FEC code is a shortened version of the triple-error-correcting Bose-Chaudhuri-Hocquenghem BCH-3 (8191,8152) code and was documented in an October 2000 revision to the ITU-T G.707 standard, which was originally approved in 1988. It inserts its 39 parity bits into the unused portion of the SONET/SDH frame's overhead, so the data line-rate does not change and standard components can be used. The frame size is fixed in time (125ms) so, as the line-rate increases, the number of bits in a frame increases. However, there are a limited number available in the frame's overhead so coding gain is limited to about 3.8dB at a BER of 10-15, sufficient for OC-48 metro but not for OC-192. Also, although the uniform in-band characteristics allow equipment interoperability, different FEC suppliers' codes are incompatible and cannot be used in the same network.
  • Out-of-band RS(255,239) FEC code was adopted from the ITU-T G.975 standard used in long-haul submarine networks and is specified for the digital wrapper of the G.709 Optical Transport Network standard (approved in February 2001). A digital wrapper removes some of the rigid overhead structure that makes SONET/SDH sub-optimal for an IP-centric intelligent optical network.

Grouping frames for existing TDM structures into "super-frames", which can then be more efficiently managed with a relatively small allocation of overhead-per-byte of data, allows the implementation of an intelligent operation, administration and maintenance (OAM) capability without materially expanding the amount of data being transmitted. This allows FEC functions to be efficiently incorporated within the digital wrapper without a significant net increase in overall bandwidth usage.

The digital wrapper simply carries bits by encapsulating the data and parity symbols with additional optical channel (OCh) overhead transport and flexible overhead mapping information designed to manage an optical network — transparently transporting traffic of all protocols — allowing equipment interoperability and efficient provisioning of bandwidth across multi-carrier networks. Unlike SONET/SDH, as the line-rate increases, the frame size remains the same in number of bytes (4x4080) rather than time, so the frame rate increases.

An RS(255,239) codeword comprises 238 data bytes plus one framing/ overhead byte and 16 parity bytes, which raise the line-rate by an overhead of 7% to 10.709Gbit/s so that the payload rate is equal to the full SONET/SDH rate (higher than the SONET/SDH payload rate). Coding gain is 6dB at a BER of 10-15, enough for most metro networks.

But, for poor installed fibre, FEC with coding gain >8dB is required, and for >6dB there are no standards, only vendor-specific solutions. For such "strong" FEC the rate overhead must be <7%, to stay within the operating range of optical transponders, and power dissipation should be <2W to fit the power budget of the OC-192 line-card. Both standard G.709 and strong FEC can then be implemented in one device.

However, there is a trade-off between performance and overhead. Higher-complexity algorithms can offer up to 10dB, but raise the line-rate by an extra 25% overhead to 12.44Gbit/s and need expensive custom components. Also, since such advanced FEC schemes run at higher line rates, some of the gain from the FEC has to offset the increased dispersion that comes from using a faster optical signal, reducing the overall advantage.

Low-cost and low-power application-specific standard product (ASSP) CMOS chips implementing FEC at 2.5 and 10Gbit/s — functionally positioned between the data source (e.g. a SONET/SDH framer) and the transceiver (see Figure 2) — are available for line-cards that can be deployed in existing add/drop multiplexers (ADMs), multi-service provisioning platforms (MSPP) and metro DWDM equipment.

The very low power requirement nullifies device implementations in processes like SiGe or GaAs due to their excessive power dissipation. Equipment makers must look carefully at the device footprint and the level of integration, as space on line-cards is limited.

The objective of chip suppliers is to increase coding gain without increasing overhead.

In September 2001 AMCC announced the Hudson (S19203), the first 10Gbit/s silicon device to support both SONET/SDH and G.709 FECs for rates up to 11.1Gbit/s. Then in June 2002 AMCC sampled its Eyemax technology, a combination of its Enhanced FEC and dispersion compensation. The first generation is implemented in a combination of the G.709-compliant Niagara (S19208) EFEC mapper and the SuperPHY family of physical layer products, which includes the 9.9–11.1Gbit/s S19211, which is the first CMOS transceiver to enable the transport of FEC-encoded 10 Gigabit Ethernet data within metro applications.

In March 2001 Multilink Technology launched its 10Gbit/s MTC6130, which supports full SONET/SDH section overhead processing for G.707 FEC, out-of-band RS (255,239)-based G.975 FEC and G.709 digital wrapper processing. The latter increases the data rate by a 7% overhead for a net coding gain of 5.5dB at 1x10-12 BER, and 6.5dB at 1x10-15 BER. But in October 2001 its MTC6131 integrated SuperFEC — based on concatenated RS(255,239) and BCH codes — increased the data rate by 25% to 12.44Gb/s for a net coding gain of 9dB at 1x10-12 and 10dB at 1x10-15 BER.

In September 2002 Multilink's MTC6134 Enhanced FEC used an RS(255,239) code with an optional proprietary FEC code with iterative decoding to give net coding gain of >7.5dB at 1x10-12 and >8.5dB at 1x10-15 BER for just the same 7% 10.66Gbit/s overhead. Use of 0.13µm CMOS gives just 3.5W of power dissipation.

Now, in early 2003, UK start-up Phyworks Ltd is sampling FEC ICs. They are fabricated as separate chips but in future could be integrated with other functions such as the physical layer or framers, it says, reducing the cost of the transmitter and receiver optics, because it becomes possible to use cheaper components designed for short-reach applications.

Phyworks will offer default G.709 FEC as well as a proprietary FEC, which has about 50% more gain but still runs at the same line rate — important, says chief technology officer Nick Weiner, for compatibility with existing commercial line-card chips.

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