Fujitsu touts 40G chip work

FEBRUARY 14, 2007 -- Fujitsu Laboratories of America, Inc. and Fujitsu Laboratories Ltd. say they have developed the industry's first CMOS IC that performs clock and data recovery (CDR) at 40 to 44 Gbits/sec. The device would be used in 40-Gbit/sec "optical serializer-deserializer modules."

FEBRUARY 14, 2007 -- Fujitsu Laboratories of America, Inc. and Fujitsu Laboratories Ltd. say they have developed the industry's first CMOS IC that performs clock and data recovery (CDR) at 40 to 44 Gbits/sec. The device would be used in 40-Gbit/sec "optical serializer-deserializer modules."

Fujitsu Laboratories presented details of the work in a paper entitled "A 40-to-44Gb/s 3x Oversampling CMOS CDR/1:16 DEMUX" at the annual International Solid State Circuits Conference (ISSCC), February 13, in San Francisco.

According to the paper, the CMOS IC recovers clock and data at rates of 40 to 44 Gbits/sec, and demultiplexes to 16x2.5 Gbits/sec. The IC also complies with the ITU G.8251 jitter tolerance mask standard, achieving BER <10(-12) with a 2(31)-1 PRBS source.

Previous ICs with similar or less functionality have been implemented in SiGe, biCMOS, and other compound semiconductor technologies. Those ICs typically dissipated three times as much power as the CMOS version, according to Fujitsu. The low power consumption, along with higher integration and reduced manufacturing cost afforded by CMOS technology, meets the requirements for developing compact form-factor 40-Gbit/sec optical SerDes modules, the company says.

"This research demonstrates the viability of CMOS for implementing the most difficult circuit blocks in future high-speed optical modules," said William Walker, vice president of the Components and Devices Integration Group at Fujitsu Laboratories of America, Inc. "In the near future, we will be able to demonstrate that the remaining blocks, such as the serializer and limiting amplifier, can also be implemented in CMOS and integrated together with the deserializer on the same IC."

The CMOS CDR, which dissipates 0.91 W while operating at 40 Gbits/sec, uses a 3X oversampling architecture. The die size is 0.8x1.8 mm and was fabricated in Fujitsu's 90-nm CMOS process. Input data is sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5-GHz clock by processing the samples.

The ISSCC paper was presented with support from Keio University in Japan, where Keio University students worked with Fujitsu's team.

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