Xilinx integrates 56-Gbps PAM4 transceiver capabilities into Virtex UltraScale+ FPGAs

Xilinx, Inc. (XLNX) says it has integrated 56-Gbps PAM4 transceiver technology into its Virtex UltraScale+ FPGAs. The new capabilities position the Virtex UltraScale+ FPGAs for use in the increasing number of designs that will leverage PAM4 to provide high-speed transmission in such applications as backplanes, optics, and high-performance interconnects.

The company demonstrated 56-Gbps PAM4 transceiver capabilities on 16-nm programmable silicon last year, and now offers the capability on the Virtex UltraScale+ devices, which leverage a 16-nm FinFET+ FPGA fabric. The IEEE has announced specification development for Ethernet applications at a wide range of transmission rates based on 50-Gbps lanes, starting with 400 Gigabit Ethernet and now including several other transmission targets (see "IEEE approves standards initiatives for 25 Gigabit Ethernet, 50, Gigabit Ethernet, 200 Gigabit Ethernet"). The OIF also has its eyes on 56-Gbps transmission for backplane applications (see "OIF launches 56-Gbps electrical interface projects"). Xilinx therefore sees the new capabilities as applicable to several end uses, including wired communications, data center networks, and wireless backhaul applications.

"Xilinx is leading the charge on transceiver technology with the infusion of 56G PAM4 into our 16nm FPGAs," said Ken Chang, vice president, SerDes Technology Group at Xilinx. "These new devices are built upon a proven FPGA foundation and are in alignment with the vast ecosystem of optics, ASICs, and backplanes soon to be deployed."

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