Communications semiconductor supplier Microsemi Corp. (NASDAQ: MSCC) says it has collaborated with Silicon Creations, a supplier of analog and mixed-signal intellectual property, to develop what the company assert is the lowest power FPGA with 12.7 Gbps transceivers, using a SerDes PHY from Silicon Creations. The new transceivers have been deployed on Microsemi's PolarFire mid-range FPGAs.
The multiprotocol PHY enables the PolarFire FPGAs to support a variety of serial protocols within wireline access, wireless infrastructure, and industry 4.0 markets. In applications related to optical communications, these include CPRI rates 1 to 9 and a mix of PON standards.
The total power for the PHYs can be as low as 4.5 mW/GB/lane, the companies say. Output random jitter is below 0.35 ps RMS at 12.7 Gbps, which make the PHYs suitable for transmitting data over OIF and IEEE 802.3 compliant short- and long-reach channels.
The PHY's ring PLL provides low area and continuous tuning range from 0.25 Gbps to 12.7 Gbps. The PLL also can operate in fractional-N mode for arbitrary frequency precision, precise spread-spectrum generation, and jitter cleaning for applications such as 10G-KR or Synchronous Ethernet, the companies say.
Other protocols/applications for which the PolarFire FPGAs can be used include PCIe Gen 1/2, JESD204B, OIF-CEI 6G and 11G, SATA, and Serial Digital Interface (SDI).
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