Frame processors provide shortcut to 40-Gbits/sec short haul

By MAREK TLALKA, Ample Communications Inc.--Products supporting four SPI-4.2 interfaces will enable 40-Gbits/sec systems using off-the-shelf components.

Sep 4th, 2002
Th 102101
Advances in silicon enable the integration of discrete component functions, including the framer, overhead processor, pointer processor, and data link logic in a single chip called a frame processor.

Products supporting four SPI-4.2 interfaces will enable 40-Gbits/sec systems using off-the-shelf components.

By MAREK TLALKA
Ample Communications Inc.

Despite delays in the introduction of new technologies as a result of the recent telecommunications economic slowdown, OC-768 (40-Gbits/sec) SONET systems are moving toward commercial deployment. Many companies are scheduled to deliver 40-Gbits/sec solutions early in 2003, and initial deployments will be in short-haul, rather than long-haul, applications.

A number of obstacles must be overcome at the photonic level before 40-Gbits/sec technology becomes a cost-effective solution for long-haul applications. However, photonic issues are not as complex in short-haul and very-short-reach applications. As a result, serial 40-Gbits/sec connections will initially be deployed in short reach intra-points-of-presence (PoPs) applications to interconnect gigabit and terabit routers and to connect routers with transport equipment such as DWDM systems.

Major network system developers are already designing systems that incorporate 40-Gbits/sec optical interfaces. According to analysts, 40-Gbits/sec optical interfaces will see initial deployment in 2003, with shipment volume reaching 3,000 ports in 2004.

As a step toward 40-Gbits/sec implementation, optical transponder vendors are completing solutions that convert a 40-Gbits/sec optical signal to a parallel electrical signal transported on a 16-bit, 2.5-MHz bus known as SFI-5. Off-the-shelf transponders are scheduled for sample availability in the latter third quarter of this year.

But what happens to data after conversion to an electrical signal presents a new set of challenges in the digital component domain. Looking at data flow from the fiber to a packet switch, a typical packet processing system consists of an optical transponder, an optional forward error correction (FEC) device, a framer, an overhead processor, a pointer processor, data engines, a network processor, and a packet switch fabric.

This architecture incorporates many power-hungry components that require a significant amount of board space. Power and board space are scarce commodities in next-generation routing platforms. Therefore, more highly integrated solutions are required to make 40-Gbits/sec systems feasible.

Gaining ground on 40-Gigabits

Recent advances in silicon technologies and migration to higher density processes have allowed leading-edge silicon vendors to integrate a number of functions into a single device known as a frame processor. The purpose of a frame processor is to identify the beginning and end of a SONET frame in the raw bit stream received from the optical transponder in the receive direction and to create a new frame in the transmit direction.

The framer portion of a frame processor performs this function. After identifying a frame, the device uses an overhead processor to process the network maintenance and administrative information embedded in the frame overhead. This information includes maintenance communications channels, such as the data communication channel (DCC), network alarms, and frame integrity information.

The next step is the pointer processing function, which finds payload channels embedded within a frame. Finally, the frame processor extracts payload data, such as IP packets or ATM cells, from the SONET frame. It then performs integrity checks on the payload and hands off the payload to a network processor unit (NPU) device for the next layer of processing.

SFI-5 and SPI-5 are the interfaces standardized for 40-Gbits/sec data applications. While transponders that support an SFI-5 interface to a frame processor will be available this year, NPUs supporting SPI-5 are still years away. Network processor developers are still working on 10-Gbits/sec NPUs and will need to realize revenues from these products before funding 40-Gbits/sec product development.

The fact that 40-Gbits/sec NPUs will not be available in the near-term poses a dilemma similar to the one faced by system developers when line speed technology migrated from 2.5 to 10 Gbits/sec. At that time, framer vendors delivered devices with an SPI-4 interface to an NPU, but NPUs were only supporting packet-over-SONET (POS) Level 3 interfaces.

As a result, system vendors were forced to build expensive converter application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) to interconnect their NPUs to 10-gigabit framers--adding significant cost to line cards in terms of FPGA cost, space, power, and development time.

Providing a better way

Fortunately, there is a better way to implement 40-Gbits/sec applications. The use of 40-Gbits/sec frame processors that support four SPI-4.2 interfaces can provide a glue-less connection to four existing 10-Gbits/sec NPUs--eliminating the need for costly converter ASICs--while supporting a native STS-768c frame.

Adding four SPI-4.2 sets of pins solves the problem at the electrical level. However, at the packet level, care must be taken to maintain packet order. A frame processor can implement a packet-ordering scheme by tagging ingress packets with sequence numbers before sending them to one of the NPUs.

This enables NPUs to re-sequence packets before sending them to the switch fabric. In the egress direction, a similar scheme can be implemented. The NPUs can tag packets with a sequence number so the frame processor can re-sequence packets before mapping them into a SONET payload envelope.

Using 40-Gbits/sec frame processors also has the advantage of flexibility. In addition to a single OC-768 data stream, typical 40-Gbits/sec frame processors alternately support four independent OC-192 (10-Gbits/sec) streams. Due to a high level of integration in 40-Gbits/sec frame processors, system developers can use a 40-Gbits/sec frame processor and four 10-Gbits/sec NPUs to develop a single-card, four-port, 10-Gbits/sec application.

Four 10-Gbits/sec transponders connect to a 40-Gbits/sec frame processor device via SFI-5s interfaces. SFI-5s are electrically compatible with SFI-5 but use only four data bits for each OC-192 interface. When 40-Gbits/sec optical transponders become cost effective, the same line card can be used for a 40-Gbits/sec application simply by replacing four 10- Gbits/sec optical transponders with a single 40-Gbits/sec version and leaving the remaining hardware and software unchanged.

In the future, when 40-Gbits/sec NPUs become available, frame processor developers will replace four SPI-4.2 interfaces with a single SPI-5 interface. This development is at least two to three years away. For now, 40-Gbits/sec frame processors supporting four SPI-4.2 interfaces will allow system vendors to develop 40-Gbits/sec-capable systems using off-the-shelf components--and have system prototypes ready by the end of 2002.

Marek Tlalka is vice president of marketing at Ample Communications Inc. (www.amplecomm.com), headquartered in Fremont, CA. He can be contacted via e-mail at mtlalka@amplecomm.com.

Figure 2 (below): By supporting four SPI-4.2 interfaces and incorporating packet ordering logic in an OC-768 frame processor, 40 Gbits/sec solutions can be implemented with four 10 Gbits/sec NPUs. This eliminates costly converter ASICs and avoids past issues encountered in OC-192 designs.

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