CEA-Leti, III-V Lab show silicon photonics transmitter

CEA-Leti and III-V Lab, a joint venture between Alcatel-Lucent Bell Labs France, Thales Research and Technology, and CEA-Leti, have demonstrated a fully integrated tunable transmitter on silicon. They say this is the first time that a tunable laser source has been integrated on silicon.

The transmitter incorporates a hybrid silicon laser, fabricated by direct bonding of III-V materials onto silicon, which exhibits 9-nm wavelength tunability, and a silicon Mach-Zehnder modulator with high extinction ratio (up to 10 dB), leading to excellent bit-error-rate performance at 10 Gbps, the team asserts.

The results were obtained as part of the European-funded project HELIOS, with contributions from Ghent University-IMEC for the design of the laser and University of Surrey for the design of the modulator.

CEA-Leti and III-V lab also demonstrated single-wavelength tunable lasers, with 21-mA threshold at 20 degrees C, 45-nm tuning range, and a sidemode-suppression ratio larger than 40 dB over the tuning range.

These results were discussed during OFC/NFOEC 2012 in Los Angeles last week.

CEA-Leti and III-V Lab believe their device represents a significant breakthrough in silicon photonics. Silicon photonics promises to lower the cost of optical devices by bringing the economics of large-scale manufacturing of CMOS to integrated photonics. One big obstacle to silicon photonics is the lack of optical sources on silicon, the base material for CMOS processing.

“We can overcome this problem by bonding III-V material, necessary for active light sources, onto a silicon wafer and then co-processing the two, thus accomplishing two things at once,” explained Martin Zirngibl, Bell Labs physical technologies research leader. “Traditional CMOS processing is still used in the process, while at the same time we now can integrate active light sources directly onto silicon.”

The heterogeneous integration process developed by CEA-Leti and III-V Lab allows III-V materials such as indium phosphide to be integrated onto silicon wafers. The fabrication process is based on 200-mm silicon-on-Insulator (SOI) wafers, which are processed on CEA-Leti’s 200-mm CMOS pilot line.

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