'Lowest-jitter' digital timing chip for OC-3 line cards

1 August 2003 Ottawa Lightwave Europe -- Zarlink Semiconductor has launched the ZL30410 digital phase-locked loop (PLL), a timing chip for access line cards operating at OC-3 rates.

Aug 1st, 2003

- Jitter performance 30% better than competing products Zarlink claims

1 August 2003 Ottawa -- Zarlink Semiconductor has expanded its portfolio of timing devices for optical networking equipment with the ZL30410 digital phase-locked loop (PLL), a full-featured timing chip claiming the industry's lowest jitter, for access line cards operating at OC-3 rates.

With the ZL30410 digital PLL and the company's analog PLLs for line cards, Zarlink is the first semiconductor company to offer both digital and analog timing devices for standards-compliant line cards in high-speed SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) access systems.

The ZL30410 timing chip generates and synchronizes clock signals used by other line card devices, such as OC-3/STM-1 framers, mappers, switches, and optical line interface chips. The company's analog PLLs connect seamlessly to the ZL30410, and support higher-speed applications by producing clock signals for OC-12/STM-4 or OC-48/STM-16 framers.

"To handle rising traffic volumes at the network edge, access systems must operate at higher speeds, and that makes their timing circuitry more complex," said Michael Rupert, marketing manager, Timing and Synchronisation, Zarlink Semiconductor.

"Our digital and analog line card PLLs are fully tested for interoperability, which reduces complexity and makes it easier for designers to comply with stringent SONET/SDH network timing standards."

Several global equipment vendors are evaluating Zarlink's line card chips for use in routers, multi-service access devices, DSLAMs (digital subscriber line access multiplexers), gateways, and next-generation DLCs (digital loop carriers).

The company claims that the jitter performance of the chip offers ratings 30% lower than comparable digital PLLs. Jitter, a cyclical variation in signal frequency, causes data errors in optical networks.

This means it can generate - without external components � the 155.52-MHz clocks that drive OC-3/STM-1 access uplinks, and the 16.384 MHz clocks that drive jitter-sensitive TDM (time division multiplex) digital switches. By contrast, clocks at these frequencies produced by digital line card chips from other vendors must be "cleaned" of jitter by external analog PLLs.

The chip generates all other clocks typically used in high-speed access line cards, including a 19.44 MHz clock, and clocks for services delivered over ST-BUS, DS1/E1, DS2, and DS3/E3. On its inputs, the ZL30410 accepts two reference clocks.

It detects the frequency of both clocks and synchronizes to any combination of 8 KHz, 1.544 MHz, 2.048 MHz, and 19.44 MHz. For more information, visit http://products.zarlink.com/profiles/ZL30410

More in Transport