SyntheSys Research launches BERTScope Stressed Pattern Generator

AUGUST 29, 2006 -- SyntheSys Research (search SyntheSys Research), developer and manufacturer of high-speed signal integrity test and measurement equipment for the computer, storage, and communications industries, has introduced its new BERTScope S Pattern Generator.

The new BERTScope S Pattern Generator allows design and test engineers to generate calibrated, stressed data for jitter tolerance testing when either the device under test (DUT) or a legacy BERT are used to measure bit error ratio. With flexible clocking capabilities from 0.1 to 12.5 Gbits/sec, it also can stress an external clock, including spread spectrum clocks (SSC) for serial bus testing.

"Our customers have been asking for a flexible product that addresses their stressed data requirements at a reasonable cost," reports Lutz Henckels, president and CEO of SyntheSys Research. "We are pleased to be offering yet another first-to-market solution that responds to their needs."

The BERTScope S Pattern Generator represents an entry point to the BERTScope product line, creating a cost-effective upgrade path to the flagship BERTScope S Analyzer, say company representatives.

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