JULY 18, 2007 -- Zarlink Semiconductor Inc. (search for Zarlink) has announced that it is sampling a range of integrated analog/digital phase-locked loops (PLLs) that it says meet all synchronous Ethernet timing requirements, including the latest recommendation from the ITU-T.
Consented in June 2007, the ITU-T G.8262 recommendation (former G.paclock) outlines the minimum performance requirements for timing devices used to synchronize networking equipment that uses synchronous Ethernet. The recommendation defines PLL performance characteristics, including wander, jitter, phase transients, clock bandwidth, frequency accuracy, and holdover.
"Zarlink is the first supplier to deliver single-chip devices meeting all synchronous Ethernet timing requirements," said Darren Ladouceur, marketing manager with Zarlink's timing and synchronization product line. "Zarlink's single-chip Ethernet timing card and line card synchronizers allow equipment manufacturers to ease integration, reduce power, and ensure compliance. As a result, customers can quickly and easily build next-generation networking equipment and retrofit existing products to support synchronous Ethernet timing capabilities."
Synchronous Ethernet technology is being deployed in DSLAMs, routers, MSSPs, PON, and multi-service access equipment to enable voice, data, video, and legacy services over a converged, high-bandwidth, synchronous Ethernet link. Previously, service providers had to maintain dedicated T1/E1 or SONET/SDH links to support time-critical services over packet networks.
Building on the previously released ZL30107 and ZL30120 Gigabit Ethernet line card synchronizers, Zarlink is now sampling its second generation of multi-rate, 1-GbE and 10-GbE analog/digital PLL products supporting all Ethernet frequencies with the option to support independent transmit and receive timing paths.
Zarlink's new Synchronous Ethernet products support both 1-GbE and 10-GbE frequencies or SONET/SDH frequencies. The devices also feature both single-ended and differential outputs.
Integrated dual PLLs in one package support transmit and receive timing paths, allowing the devices to seamlessly convert backplane and PHY clocks, Zarlink says. In the transmit path the products support rate conversion from standard telecom or Ethernet frequencies and provide jitter attenuation to generate a low-jitter Ethernet clock for the PHY. In the receive path the products rate convert the synchronous Ethernet recovered clocks to the backplane frequency, which then feeds back to the system timing card. In comparison, competing approaches would require multiple devices to implement transmit and receive timing paths, the company asserts.
Zarlink's synchronous Ethernet products are designed to support multiple input references, hitless reference switching, holdover, low-jitter Ethernet outputs, and programmable clock and frame pulse outputs. Zarlink says its timing card products also provide wander filtering meeting G.8262 requirements.
Zarlink's expanded family of Synchronous Ethernet timing products is now sampling. Zarlink is also sampling new devices that combine synchronous Ethernet and IEEE-1588 functionality for applications that require accurate timing frequencies and time-of-day capabilities.
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