Xilinx announces interoperability with IBM SerDes technology
22 December 2003 San Jose, CA Lightwave--Xilinx today announced successful interoperability testing of the IBM high speed SerDes (serial/deserializer) core with Xilinx's Virtex-II Pro 3.125 serial transceivers.
22 December 2003 San Jose, CA Lightwave-- Xilinx today announced successful interoperability testing of the IBM high speed SerDes (serial/deserializer) core with Xilinx's Virtex-II Pro 3.125 serial transceivers. With Xilinx field-programmable gate arrays (FPGAs) and IBM ASICs often on the same boards, the interoperability testing significantly reduces overall product time-to-market by allowing customers to focus on design issues rather than verifying electrical compliance. Applications now enabled include high speed interface requirements for Fibre Channel, PCI Express, Serial Rapid I/O, Serial ATA, Serial Attached SCSI, 10 Gigabit Ethernet, and Optical Internetworking Forum (OIF) interfaces.
"The interoperability of the IBM and Xilinx SerDes cores, coupled with Xilinx's industry standard interface compliance is a testament to the robustness of the two companies' SerDes designs," said Bill Van Duyne, director of Field Applications for IBM Microelectronics. "IBM ASIC customers will find that not only do Xilinx FPGAs lend themselves to needed board logic, they can also extend ASIC product life cycles given their flexibility which allows additional functionality to be added later."
"IBM SerDes interoperability with Xilinx high speed serial transceivers is key to ensuring the confidence of designers who need to add the flexibility of a Xilinx FPGA to complement their ASIC design," said Jerry Banks, director of Global Alliances at Xilinx. "Interoperability testing now reduces the need for interoperability testing later in the design cycle."
The test and verification interoperability plan was designed to ensure full and rigorous electrical interoperability testing of the two cores. Both SerDes technologies were tested interactively for transmit and receive functions Additionally, the signaling was performed asynchronously in order to most faithfully reproduce an actual functional environment. A variety of pseudorandom test patterns were used in order to mimic actual data traffic. Furthermore, both backplane and point-to-point signaling were characterized. In the end, no bit errors were logged between the two devices in any of the test cases.
The IBM high speed SerDes family of cores support data throughput rates from 125 Mbits/sec to 6.4 Gbits/sec. With sophisticated equalization circuitry and the ability to implement up to 200 links on a single chip, a single IBM ASIC in 0.13 micron can support 2.5 Tbits/sec of effectively errorï¿½free transmission for all popular high-speed serial transmission standards.
Xilinx Reference Design Alliance Program
The Xilinx Reference Design Alliance Programbuilds collaborations with industry leading semiconductor and design companies to develop reference designs for accelerating our customer's product and system time-to-market. IBM is a member of the Xilinx Reference Design Alliance Program.