Stephen Hardy, Editorial Director and Associate Publisher
Next to a venture capitalist with deep pockets, an emerging carrier is an optical-networking startup's best friend. While incumbent carriers already have a significant investment in existing equipment to protect, carriers just starting to roll out their networks have a much greater opportunity to try new network architectures and technology.
Of course, just as systems startups view these emerging carriers as the seed beds from which they will eventually harvest their first big sales, these optical-networking companies themselves could be viewed as an emerging market for merchant silicon vendors. With a clean slate on which to start their designs, could these companies be tempted to shun ASIC-based approaches and partnerships with ASIC vendors? Con versations with representatives from three of these optical-networking newcomers reveal the battle between ASICs, FPGAs, network processors, and other off-the-shelf chips for dominance in this space appears far from over. But ASIC approaches have not fared well in some early skirmishes.
With a jaw-dropping initial public offering and a growing list of customers, Sycamore Networks (Chelmsford, MA) serves as the poster child for the high-flying optical-networking startups. The company has placed its SN 8000 and SN 6000 Intelligent Optical Nodes as well as its SN 16000 Intelligent Optical Switch in the networks of such carriers as Williams, Enron Broadband Services, Global NAPs, and LD Com.
One key to Sycamore's success has been the ability to shrink the functionality of what had previously been contained in a standalone system into a board. Perhaps surprisingly, such feats of design skill have not required proprietary ASIC development. In fact, Sycamore shuns proprietary silicon as a matter of corporate philosophy. The support of outside sources such as silicon vendors allows Sycamore to focus on its strengths.
"We do the design and are responsible for the product in every shape and form," says Rick Barry, Sycamore's chief technical officer. "But we buy all the components off-the-shelf, and we have other people do the labor for us in terms of manufacturing."
A reliance on off-the-shelf technology doesn't mean that Sycamore will settle for plain vanilla. "In terms of the silicon vendors, we worked with them on their next-generation products. So we like to use off-the-shelf-but we also would like to be the first to use the off-the-shelf and partner with somebody to develop something that every one needs," Barry ex plains. "So we're not really interested in doing something proprietary. We're more interested in being the first to use something that later lots of people can use because we want the volumes up there."
In evaluating potential partners, Sycamore used fairly basic criteria: Did the vendor have the capability to deliver the performance required now, and did it appear to have the horsepower to keep up with Sycamore's future needs? Barry reports that his company, which has systems that will merge OC-48 signals into OC-192 pipes, had no problems finding FPGAs and other off-the-shelf silicon that could meet system performance requirements.
While some companies tout their ASIC expertise, Barry feels that the purported advantages of proprietary ASIC-based designs are overrated. "An ASIC only gives you a three-month lead these days-depending on the application. I've not personally found that ASICs are that far ahead in our field in the last two years than chips from some of the advanced players like AMCC, Vitesse, and PMC-Sierra, for instance," he says.
ASICs don't provide much of a time-to-market advantage, either, Barry claims. "If you look at what it takes to put out the next generation of a product, whether you're going from [OC]-48 to -192 to -768, there's a lot of different components that go in there," he continues. "So the mere fact that you've got one part that you've done an ASIC on isn't going to necessarily help you get to market faster." Barry admits that he has seen other companies use ASICs to provide better levels of integration on their boards based on their particular system architecture. However, he doesn't believe that such integration provides a true strategic advantage in the marketplace-at least not one that lasts.
As far as future requirements, Barry says his company is looking for advancements in four areas: transport, switching, monitoring, and interconnect. So far, the standard silicon vendors appear ready to deliver what's required.
"In the last year or two, [some] of the most important technologies for optical networks have been electrical. And that has been forward error correction and, for lack of a better term, 'SONET processors,'" Barry claims. "There are a num ber of solutions out there for both of those right now that enable you: one, to go farther using forward error correction with custom off-the-shelf solutions rather than ASICs, and on the second one, SONET processors, they enable you to essentially do the functionality of an add/drop node in a chip."
Forward error correction addresses the transport section of Barry's wish list. Other areas include better performance and higher speeds out of chips that perform such functions as clock recovery and laser driving. Integration-such as moving SERDES functions into re ceivers-also is a requirement.
One might envision that the new generation of network-processor chips might find use for transport. "I think it's very exciting stuff," he says of these offerings. "Whether or not it's going to find applications in the optical-networking space-at this point, I'll reserve judgment."
The SONET processors can fill a void in both transport and switching. Off-the-shelf chips that perform crossconnect functions and packet processing also will play a role in future switching applications, says Barry. A standard silicon switch offering that supports 10-Gbit/sec speeds would also be welcomed.
Monitoring advances will be needed across the board, says Barry, from SONET and packet monitoring to optical signal monitoring. Barry sees a role for DSPs in future applications of this type. "People are now building very compact optical spectrum analyzers. But to make that work, you really need a DSP to analyze the data," he explains. As far as interconnect is concerned, continued advances in vertical-cavity surface-emitting lasers (VCSELs) to support optical backplanes and very-short-reach (VSR) applications are on the horizon.
Overall, speed appears to be a primary concern when it comes to off-the-shelf silicon. According to Barry, OC-48 chips can be found now and OC-192 by the end of the year. But optical-networking companies with an off-the-shelf philosophy will have to wait until next year to enter the race to deliver OC-768 capabilities, he feels.
Alidian Networks (Mountain View, CA) also designed its family of Optical Service Network (OSN) equipment for the metro market without the use of proprietary ASICs. Unveiled in April, the equipment family includes the OSN 4100, 4200, and 4800, which provide support for multiple transmission protocols and add/drop functionality on a scale from two to 32 OC-48s. Two CLECs, Enkido and Everest Broad band, have committed to conduct trials of the OSN product line.
Alidian's design team started with an agnostic approach to the ASIC versus FPGA issue, according to Ted Rado, the company's director of marketing. The Alidian engineers decided to finish the basic design of the system in-house, then see which technology would be necessary to meet their requirements.
That said, the team's agnosticism was somewhat artificial. "Certainly the leaning here was that we'd rather do things in an FPGA, initially because of the time-to-market issues associated with FPGAs-FPGAs allow you to get things done quicker and make design iterations much faster," reveals Rado, who worked for five years at an FPGA company before coming to Alidian.
The decision point came late last year, when the designers realized they would need an FPGA that could support hundreds of thousands of gates as well as meet their performance requirements. "I think the densities of the newest FPGAs are rather large- going up to a million FPGA gates in a product," says Rado. "But the big question is what the performance is going to be compared to an ASIC."
According to Rado, the Alidian team "breathed a huge sigh of relief" when a new generation of FPGAs entered the market just as they were about to make a decision. "I think we were very fortunate in the fact that there were new FPGAs that were coming out on the market that hit our criteria. If we had been at that same stage three or four months earlier, it probably wouldn't have happened-it would have had to have gone to ASIC," he says.
Besides saving the company an estimated six months in development time, the move to FPGAs also kept the design resources to a manageable size. "One of the advantages of being able to work on an FPGA is that the number of people you need is quite a bit less than if you're doing an ASIC, because the simulation and verification aspects are a lot easier in FPGAs," Rado explains.
More than one vendor had potentially adequate FPGAs, so Alidian was able to compare and contrast offerings. "We made a decision based on availability of the product, price of the product, and what their road map was," explains Rado. The "road map" spelled out each FPGA's expected evolution-from such issues as when they might use 0.18-micron processes and how steeply the density curve was expected to climb. "It's important to see the road map that they're offering, because we know that our product is going to get more and more advanced. We're going to need to place more and more functionality into the FPGA product. And we need to make sure that their roadmap coincides with ours in terms of where the performance of their product is going to be," he concludes.
Rado declined to reveal which vendor won Alidian's business, other than to say the company "is one of the big two or three." He also declined to reveal the network-processor company with which Alidian partnered to create a unique application for a standard network-processing chip. "It's almost like a semi-ASIC type of thing. But all the risk associated with 'is the silicon going to come out' wasn't an issue, because the silicon remained the same. It's just all the firmware and code that you're writing for it is something that we worked with the network-processor company to kind of alter for our application," Rado says.
The use that Alidian made of network processors is unique, Rado believes. However, he expects other systems houses will soon incorporate this technology into their systems. Choosing the right vendor can be trickier than it first appears, however. With network-processor vendors getting snapped up left and right by larger firms, keeping the supply chain open can prove dicey at best. "We've seen it just recently," cautions Rado. "One of our competitors in our market was using a network processor from a privately held company that was bought out. That product now is off the market, and they're about six months behind from where they were before that company was bought out."
Like Barry, Rado feels that the factors that made ASICs necessary in some applications don't necessarily apply to all optical-communications systems. The realities of the optical-networking space bring new variables to the design equation. "One of the things that all of these optical-networking companies are dealing with is that the cost of the product is mainly in the optics," Rado explains. "And so the cost issue associated with whether you go with an FPGA or an ASIC is kind of a non-issue for products like this. Because when you roll up the total cost, whether you're spending a couple of hundred dollars more for an FPGA versus an ASIC, it doesn't affect the total cost of the product."
For optical-networking companies like Alidian, the primary criteria for evaluating a technology include time-to-market, size of the design, performance of the design, and cost. Rado says that time-to-market is the number one criterion, which he believes favors FPGAs. FPGAs also can hit the size criterion, meet most performance targets, and come close enough in cost that this factor doesn't much matter.
However, Rado doesn't rule out the possibility of moving current FPGA functions into ASICs in future generations of Alidian's equipment. While a desire for cost reduction would provide one motivating factor, performance issues will prove paramount. "Over time, I think it will be interesting to see how well FPGAs will keep up," offers Rado. "Because, if they can keep up with the continuing performance demands of our new designs, then we'll definitely go that route. But if they can't keep up on the performance side, then ASICs will be the way we do things."
While there appears to be growing support for merchant silicon as the linchpin of optical-networking equipment design, not every company is ready to fire its ASIC engineers. For example, Cyras Networks (Fremont, CA) made extensive use of proprietary ASIC technology in the design of K2, a new metro switching and transport product unveiled late last month.
The requirement for speeds as high as 10 Gbits/sec and a fabric that can accommodate 768x768 STS-1 switching drove the reliance on ASICs. "In order to implement that kind of bandwidth and speed, you need to have silicon implemented with a very high clock rate," explains Sunil Tomar, vice president of hardware at Cyras. "So it was pretty obvious that you will need something to run chips in the hundreds of megahertz range. FPGAs clearly are not there to be operational at that range."
Tomar acknowledges that FPGA suppliers have made significant advances in both speed and gate size. However, he's not convinced that these advances have progressed as far as vendors claim. "FPGA salespeople and marketing people claim that they have reached speeds of 150 MHz. When I typically take that and implement them, I get half that speed," he asserts.
He reports a similar experience with gate-count claims in the millions. "I think you can comfortably do a half-million-gate type of FPGA these days, half-a-million to three-quarter million," Tomar says.
With a performance requirement of several hundred megahertz and a density well over a million gates, the decision to stay in ASIC therefore required little soul searching. "Clearly FPGAs wouldn't have cut it, and I wasn't prepared to wait for another five years until FPGAs could catch up. So it was pretty obvious that we had to do silicon ASICs," Tomar states.
The next step in the design process involved finding an ASIC partner. The Cyras designers wanted to do their own logic design, including RTL coding and synthesis, and then turn to an outside vendor for implementation. The company chose LSI Logic for the role, based on the firm's reputation and its experience in the development of serial backplane technology, which Tomar wanted to borrow from storage area network applications.
However, while ASICs lie at the heart of the design, Cyras didn't shun FPGAs entirely. "When we did our analysis as to what we should implement in ASIC and what we should leave for FPGAs, we came to a conclusion that we can really collapse a lot of functionality into ASICs, but I don't think we could collapse the whole thing into an ASIC," Tomar offers. "So clearly, there were areas that made sense that we should be implementing this part of the logic on other boards in FPGAs."
One role FPGAs filled involved expanding the capabilities of off-the-shelf protocol implementation chips. "Suppose on a board we're using five off-the-shelf chips," Tomar says. "They would give you the basic functionality, but for the few different things our company is doing which are unique, you need to implement that logic in a separate FPGA. So that sense, we'll pull out the signals from these chips, then implement logic that will enhance the feature set of our product."
Cyras chose Xilinx as its FPGA vendor. But the use of merchant silicon won't end there. Cyras is in discussions with several network-processor suppliers in search of chips for future generations of products. The choice of product hinges on more than hardware functionality.
"A lot of it is how are you going to write firmware for it? What is involved in writing the software for it, and how many resources do we have to allocate?" Tomar explains.
Tomar reports significant differentiation among network-processor vendors in terms of capabilities and support. He predicts that Cyras will finish sifting through the various offerings by the second or third quarter of this year, in hopes of having something it can use by the end of the year.
Tomar says that the protocol-agnostic nature of many network-processor offerings should prove extremely useful in future equipment designs, particularly as carriers attempt to provide multiprotocol services or as systems vendors attempt to sell the same product to multiple carriers who have standardized on different transmission protocols.
With new optical-networking companies appearing almost monthly, it seems logical to assume that a wide variety of design approaches will mark this space. Clearly, however, the use of merchant silicon is an approach that will become all the more common- particularly as time-to-market drives equipment design.
"There are obviously some companies in the optical-networking space now that have gone the ASIC route from day one. And I can't think of one company that started within three to six months of when Alidian started that has a product out, whereas Alidian does have a product out," Rado claims.
Still, the desire to increase the speed of design cycles may run afoul of the realities of similar increases in network speed and demands for improved performance. If FPGA and other off-the-shelf chips can't keep pace with system requirements, companies like Sycamore and Alidian may be looking for ASIC engineers of their own.
This article appeared in the June 2000 issue of Integrated Communications Design, Lightwave's sister publication.