June 5, 2006 Santa Clara, CA -- Fujitsu has selected PMC-Sierra's metro transport semiconductor products for its flagship metro optical products: The FLASHWAVE 7500 Reconfigurable Optical Add/Drop Multiplexer (ROADM) and the FLASHWAVE 4500 Multi-Service Provisioning Platform (MSPP).
The FLASHWAVE 7500 ROADM integrates SONET add/drop multiplexer (ADM) functionality onto individual Flexponder interface cards using PMC-Sierra's CHESS III chipset. The complementary FLASHWAVE 4500 MSPP utilizes not only the CHESS III chipset but also PMC-Sierra's CHESS wideband chipset. The CHESS wideband chipset is used to achieve high-capacity VT1.5 grooming, as required by next-generation MSPPs to map data and TDM traffic into SONET/SDH tributaries.
The CHESS family enables Fujitsu to provide distributed, scalable metro transport equipment with reduced power, cost, and complexity, even as service providers demand higher levels of integration and flexibility, say PMC-Sierra representatives. These benefits improve fiber efficiency, reduce capital and operational costs, and provide service providers with the ability to introduce and more effectively manage both new Ethernet and existing T1/E1 services.
"Fujitsu continues to deliver best-in-class platforms for the optical networking market," asserts Minoru Takeno, general manager of the Photonics System Group at Fujitsu. "PMC-Sierra's CHESS portfolio offers highly integrated framers, scalable non-blocking switch fabrics and powerful pointer processors. PMC-Sierra's solutions best enabled us to meet customers' emerging needs, which are being driven by triple-play service deployment. Key performance innovations, best-in-class analog and mixed-signal technology, and unmatched customer support clearly distinguish PMC-Sierra from other vendors."
PMC-Sierra's CHESS III is the foundation chipset used to build the new generation of metro transport equipment. It offers a range of STS-1/AU-3Icross-connect solutions as well as a highly integrated framer solution for MSPPs and ROADMs, report company representatives. The CHESS III chipset consists of the following devices:
• TSE-Nx160, a 64-port cross-connect device that enables single stage non-blocking cross-connects to scale from 160 Gbits/sec to 640 Gbits/sec;
• TSEA240, a 96-port cross-connect device that reduces the software complexity of A automatic protection switching using Message Assisted Protection Switching (MAPS) technology; U
• TSE 120, a 74-port cross-connect deviceIoptimized for lower bandwidth, lower cost applications;
• ARROW-2x192, a highly integrated channelized 20-Gbit/sec framer that supports eight ports of OC-48/STM-16 or two ports of OC-192/STM-64; and
• ARROW-1x192, a highly integrated channelized 10-Gbit/sec framer that supports four ports of OC-48/STM-16or one OC-192/STM-64Eport.
The CHESS Wideband chipset is a highly integrated VT/TU grooming set that enables cost-effective in-service upgrades to (micro)MSPPs, MSPPs, and Optical Cross Connect systems.
The CHESS Wideband chipset consists of the following devices:
• WSE 40, an 18-port wideband cross-connect, device that reduces the software complexity of automatic protection switching using MAPS technology;
• WSE 20, a 10-port wideband cross-connect device optimizedIfor lower bandwidth, lower cost applications; and I
• TUPP 9953, a SONET/SDH tributary unit payload processor for 9953 Mbits/sec.