Silicon Labs' clock multiplier provides any-rate frequency synthesis

March 28, 2007
MARCH 28, 2007 -- Silicon Laboratories Inc. says it is making available the industry's first jitter-attenuating clock multiplier IC that generates any output frequency from any input frequency with 0.3-psec jitter performance.

MARCH 28, 2007 -- Silicon Laboratories Inc. (search for Silicon Laboratories) says it is making available the industry's first jitter-attenuating clock multiplier IC that generates any output frequency from any input frequency with 0.3-psec jitter performance.

The Si53xx Any-Rate Precision Clocks product family features nine devices leveraging Silicon Laboratories' DSPLL technology to offer a broad portfolio of reconfigurable, frequency-agile precision clock sources. The Si53xx any-rate capability addresses high-performance applications such as next-generation networking, telecommunications, wireless base stations, test and measurement, HDTV video, and high-speed data acquisition. The Si53xx family consists of four any-rate clock multipliers (Si5322, Si5325, Si5365 and Si5367) and five any-rate clock multipliers/jitter attenuators (Si5316, Si5323, Si5326, Si5366 and Si5368).

The company says the high-performance Si53xx is the first clock multiplier to generate any output frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from any input frequency between 2 kHz and 710 MHz. The product family features an integrated loop filter with selectable bandwidths, allowing designers to change the loop bandwidth without changing components and enabling jitter performance optimization at the application level.

A rich set of on-chip features reduces the bill-of-materials (BOM) while optimizing jitter performance. The Si53xx includes an ultralow phase noise, frequency-agile voltage-controlled oscillator (VCO), loop filter, phase detector, divider, and buffers. Traditional PLL designs require discrete components, creating noise entry points between circuit elements. By eliminating the noise entry points, the Si53xx simplifies the task of achieving ultralow jitter performance. Additionally, the Si53xx family supports up to four clock inputs and five differential clock outputs, eliminating the need for external multiplexers and clock distribution buffers traditionally used in complex timing subsystems of modern communications equipment.

The devices simplify the design and supply chain issues of modern timing architectures. Unlike traditional PLL implementations that only operate over a limited frequency range, the Si53xx family can be digitally reconfigured to operate over a broad range of frequencies, removing the need for multiple expensive voltage-controlled crystal oscillators (VCXOs) or voltage-controlled SAW oscillators (VCSOs) and easing design reuse. The ICs also support hitless switching to absorb phase differences between input clocks during a clock switchover. In addition, the Si53xx uses standard IC manufacturing technology, which can reduce lead times to 4 weeks compared with the potentially long lead times associated with VCXO- and VCSO-based clock circuits.

"The any-rate capability of the Si53xx family broadens the addressable market of our timing solutions," says David Bresemann, vice president of Silicon Laboratories. "The combination of the any-rate precision clock family and our oscillator and voltage controlled oscillator products creates the industry's most comprehensive portfolio of frequency-flexible, low-jitter timing solutions."


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