Inphi intros 12.5-Gbit/sec 1:8 demus with latched comparator input

JANUARY 8, 2008 -- The 1385DX is designed to enable test and measurement (as well as defense and aerospace designers) to develop high-speed data acquisition front ends and to deserialize high speed signals.

JANUARY 8, 2008 -- Inphi Corp. (search for Inphi) has announced the 1385DX, a 12.5-Gbit/sec 1:8 Demultiplexer with Latched Comparator Input operating at bit rates from DC to 12.5 Gbits/sec. Part of the High Speed Logic family of devices, the 1385DX, with its high-sensitivity latched comparator input and auto-synchronizing demultiplexer, is designed to enable test and measurement (as well as defense and aerospace designers) to develop high-speed data acquisition front ends and to deserialize high speed signals.

"Validation of multi-gigabit serial interfaces in the next generation server memory architecture is difficult with extremely stringent performance and signal integrity requirements," said Levi Murray, vice president, technology enabling and infrastructure development for Advanced Micro Devices. "Inphi has designed the 1385DX to enable us to properly characterize and validate these interfaces and to meet our performance and time-to-market objectives in a cost-effective manner."

The 1385DX features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analog signals and demultiplex them to a lower data rate for post-processing via a low-speed FPGA or ASIC. Additionally, the high bandwidth input supports digital signals up to 12.5 Gbits/sec, which are latched and deserialized to an eight bit parallel output bus. The 1:8 deserialization, coupled with an on-chip synchronization circuit and adjustable output levels, is designed to allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers.

The 1385DX accepts a single external clock at up to 12.5 GHz that samples the input signal from the high-bandwidth comparator. Internally generated clocks are used for demultiplexing the latched input signal to an eight-bit parallel data bus. The device outputs a full-rate clock (one-eighth of the input clock) or half-rate clock (one-sixteenth of the input clock) as determined by the CLKSEL input.

The DEMUX's built-in synchronization circuit enables two or more 1385DXs to be automatically synchronized using a master/slave mode, in which the slave DEMUX synchronizes to a signal (CK16) from the master, or a slave/slave mode, in which both 1385DX's are synchronized to an external master clock (one-sixteenth of the input clock frequency). Synchronization occurs within at most 152 periods of the input clock.

Other benefits include low deterministic (10 psec pp) and random jitter (2 psec RMS), and fast rise and fall times of 75 psec; automatic synchronization of multiple 1385DX demultiplexers; differential CML outputs with common mode adjust and 500 mVpp differential amplitude; and high-sensitivity latched comparator input with front-end bandwidth of 14 GHz.

The 12.5 Gbps 1:8 Demultiplexer with Latched Comparator Input operates from a standard +3.3-V power supply. It is currently shipping in pre-production quantities in an 8x8 mm QFN package or on an evaluation board with SMA connectors, and full production is expected to begin in Q1 2008.

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