Lattice Semiconductor debuts lowest power 10-Gbit/sec SERDES transceiver

23 June 2003 Hillsboro, OR Lightwave--Lattice Semiconductor Corporation today announced the availability of the industry's lowest power 10-Gbit/sec SERDES transceiver based on 0.13-micron CMOS technology. Designed for SONET OC-192 and 10 Gigabit Ethernet applications, the XPIO 110GXS consumes only 0.8 W of power and supports optical transponder modules such as the 300-pin multisource agreement (MSA) as well as those for 10-Gbit/sec small form- factor pluggable (XFP) applications.

23 June 2003 Hillsboro, OR Lightwave--Lattice Semiconductor Corporation today announced the availability of the industry's lowest power 10-Gbit/sec SERDES transceiver based on 0.13-micron CMOS technology. Designed for SONET OC-192 and 10 Gigabit Ethernet applications, the XPIO 110GXS consumes only 0.8 W of power and supports optical transponder modules such as the 300-pin multisource agreement (MSA) as well as those for 10-Gbit/sec small form- factor pluggable (XFP) applications. The high performance transceiver meets both SONET and Ethernet jitter requirements.

Previous Lattice field programmable system chip devices, such as the ORSO82G5 and ORT82G5, support 10-Gbit/sec traffic using four channels of 2.5 to 3.125 Gbit/sec SERDES, depending on the encoding/decoding scheme utilized. The new XPIO device generates and receives 10-Gbit/sec clock/data streams (full duplex) utilizing CML signaling over a single channel, reducing the number of connections needed. Offering a continuous operating range from 9.953 to 10.709 Gbits/sec, the low-power transceiver is well suited for SONET OC-192 and 10 Gigabit Ethernet applications.

The new device can also be used in 200-pin MSA- or 300-pin MSA-based optical transponder modules. The device supports 16:1 serialization and 1:16 deserialization with a parallel LVDS data range from 622 to 670 Mbits/sec supporting the Optical Internetworking Forum's SFI-4.1 and 10 Gigabit Ethernet's XSBI standards. An on-chip low-jitter PLL generates all required clocks based on an external reference clock of 155.52 MHz or 622.08 MHz. The integrated limiting amplifier further enhances design flexibility and improves the bit-error rate.

The device achieves its extremely low power consumption through a combination of advanced 0.13-micron CMOS technology, reduced 1.3V core and 2.5V I/O voltages, and proprietary circuit design techniques. As a result, the devices typically consume only 0.8 W when operating at 10 Gbits/sec, lower than any competitive transceivers currently available or announced, according to the company.

Samples of the XPIO 110GXS device are available now, with volume production scheduled for the second half of 2003. The device is packaged in an15x15mm, 269-ball flip-chip BGA package. Prices for the device are projected to start at $79.00 in 5,000 piece quantities for delivery in the first half of 2004. The ordering part number is XPIO 110GXS-01CF269C. XPIO 110GXS evaluation kits are available through authorized Lattice distributors at a price of $4999.


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