While network-processor vendors contract, capabilities expand

As if to illustrate why the name of the Network Processors Conference West will change next year, most of the action at October's show in San Jose, CA, focused on such chips as network search engines and switch fabrics. Analysts predict that when the event returns next year as the Network System Design Conference, the number of vendors in this space will have shrunk. However, the capability of processors and related devices continues to expand.

Network-processor units (NPUs) are programmable devices that provide such Layer 3 to 7 functions as classification, modification, and forwarding for Ethernet and IP packets and ATM cells. Since they don't have the capabilities of some of the complex ASICs they are designed to replace, NPUs frequently link to network search engines that access lookup tables or to traffic-manager chips that help provide quality of service (QoS) functions.

Observers first expected NPUs would find homes in core networking systems, particularly as networks moved to IP. But due to a combination of the difficulty in developing devices that could keep up with the core's 10-Gbit/sec line requirements and the need for packet processing closer to the user, NPUs have found most of their wireline applications in edge devices and DSL access modems (DSLAMs). However, 10-Gbit/sec devices have begun to appear, and it is at this line rate that startups such as Bay Microsystems, EZchip, and Xelerated (which has developed a device capable of operating at 40 Gbits/sec) have their best shot at finding a place among the established vendors currently dominating at lower line rates. The market leaders the startups hope to unseat include AMCC, Intel, Agere Systems, Motorola, and IBM (which has stopped developing NPUs but enjoys 15% of the market, according to Linley Group research).

Xelerated (Burlington, MA) made one of the few new NPU introductions at the Network Processors Conference West when it unveiled the X11 network processor. While it operates at half the speed of Xelerated's original X10q device, the 20-Gbit/sec X11 features an enhanced pipeline architecture that integrates 10-Gbit/sec MACs and a XAUI interface. Improved buffer management will obviate the need for traffic managers in some enterprise applications, according to the company's vice president of marketing, Gary Lidington. Xelerated has targeted the device at mid-range enterprise systems and metro Ethernet devices. The chip will sample in next year's third quarter.

Agere (Allentown, PA) announced an NPU for ATM voice applications. The APP100 processes voice signals at up to 622 Mbits/sec; it can handle 32,000 voice channels simultaneously. The chip began sampling last month, and production quantities should be available next April. Meanwhile, Bay Microsystems (Santa Clara, CA) announced a classification processor, the Biscayne, which complements the company's Montego 10-Gbit/sec processor. The latter device provides NPU functions, traffic management, and segmentation and reassembly. Bay Microsystems will offer 166- and 100-MHz versions of the Biscayne for less than USD300 in volume quantities. Samples will be available in the next quarter.

Perhaps the most interesting news at the show, however, centered on the evolution of technology for network search engines, which aid in forwarding and policy lookup activities. Ternary content-addressable memory (TCAM) devices have dominated this space; IDT (Santa Clara, CA) discussed its new 18-Mbit TCAM with dual LA-1 interfaces in a presentation during the show. However, algorithmic approaches to lookup—which promise lower power requirements than TCAMs as well as lower costs when multiple chips are necessary—appear to be finally ready for application.

Xelerated uses algorithmic lookup technology in its new X11 NPU; Procket Networks (Milpitas, CA) takes a similar approach to the NPU at the heart of its PRO/8000 router. However, separate search engines that leverage algorithms are approaching the sampling stage. Xelerated introduced a pair of longest prefix match lookup engines based on Mtrie algorithms for use with its X10 device. The company will offer the engines, which leverage DRAMs, in the form of FPGA images for the Xilinx Spartan-III.

HyWire (San Jose and Netanya, Israel) will offer cores for FPGAs as well as chips under the HyCognito family name. The technology supports up to 400 million searches per second in high-end applications. The cores, designed for applications at about 2.5 Gbits/sec and below, are slated to be available next month. The company expects to offer 10-Gbit/sec devices in hardware in next year's second quarter.

Cypress Semiconductor (San Jose), which makes TCAMs, will extend its product line with the Sahasra 50000 algorithmic search engine. While HyWire asserts that algorithmic search engines will meet all lookup applications, Cypress believes that devices such as the Sahasra are best for low-speed forwarding lookup applications, which leaves policy lookup functions for TCAMs. Cypress will make samples of its algorithmic device available in the next year's second quarter.

Meanwhile, the switch-fabric space also altered at the show. AMCC (San Diego, CA), which recently purchased IBM's Packet Routing Switch (PRS) group, unveiled the first new device from its acquisition, the PRS 80G chipset. The chipset includes the PRS C48X and C192X switch-fabric interface devices. As its name implies, the PRS 80G set will offer 80 Gbits/sec of switching in a two-chip configuration; one-chip designs to support 40 Gbits/sec also are possible. The switch fabric will sample in the next quarter, with the interface devices arriving the following quarter.

For its part, startup TeraChip (San Jose) demonstrated a 320-Gbit/sec configuration using two of its TCF16X10 160-Gbit/sec fabrics. The demonstration featured AdvancedTCA fabric boards. Startup Fulcrum Microsystems (Calabasas Hills, CA) discussed its Nexus switching technology, which it will aim at board-level switching among NPU and other resources on the same line card. Fulcrum will market the SPI-4.2 System Interconnect as the PivotPoint, which will enable devices that previously had to be linked in a daisy-chain configuration to interact as a reconfigurable pool of resources. First customer silicon is slated to appear by the end of this month.

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