Aeluros enhances integrated EDC/10G PHY/SerDes for 10GBASE-LRM applications

Dec. 18, 2006
DECEMBER 18, 2006 -- Aeluros claims its EDC technology has been tested against various ROSAs with different "linear" transimpedance amplifiers from different vendors to ensure interoperability with configurations that would be encountered in X2 optical modules and SFP+ line-card applications.

DECEMBER 18, 2006 -- Aeluros (search for Aeluros) today announced the availability of its second-generation 10-Gigabit Ethernet (GbE) PHY/SerDes devices with integrated electronic dispersion compensation (EDC) for 10GBASE-LRM (search for 10GBASE-LRM) applications.

Targeted for both XAUI-based optical modules and the emerging SFP+ systems applications, the new devices are built upon the earlier generation of the Puma AEL1003, say company representatives. Like the Puma AEL1003--a highly integrated device with full PCS, PMA, and XGXS sub-layer functionality--the new devices feature what the company claims is the industry's lowest power dissipation.

This latest generation of integrated EDC/PHY/SerDes devices from Aeluros incorporates performance enhancements to the original EDC engine that was demonstrated at OFC/NFOEC in March 2006. Enhancements include improving the robustness of the EDC algorithm to address not only the standard stress test pulses defined in the IEEE 802.3aq specifications for 10GBASE-LRM, but also more stringent corner cases that could simulate real-world deployment situations and identify the real breadth of the EDC engine's performance characteristics, says the company.

Aeluros' EDC technology has been extensively tested against various receive optical sub-assemblies (ROSAs) with different "linear" transimpedance amplifiers from different vendors to ensure interoperability with a variety of configurations that would be encountered in X2 optical modules and SFP+ line-card applications. In addition to the standard IEEE stress tests available through optical testers, Aeluros has tested its EDC technology with internally developed stress tests and with high-DMD fiber combined with pre-production SFP+ modules. Aeluros intends to make these tests available to its systems-customers.

"We have focused on developing a very robust EDC engine for our integrated PHY/SerDes devices,"Icontends Stefanos Sidiropoulos, co-founder and CEO of Aeluros. "With a robust EDC function suitable for XENPAK/X2 modules and SFP+-based line-cards, Aeluros is well positioned to address the requirements of both existing and emerging systems architectures," he says.

Samples of the device will be available to Aeluros' modules customers in 15- x 15-mmI BGA packages and to its line-card customers in 10- x10-mm packages to allow for high-density architectures driven by the emerging SFP+ based system architectures.


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