Zarlink's analog/digital PLL provides synchronization at physical layer
MARCH 1, 2007 -- The ZL30107 chip, which is in volume production now, provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures.
MARCH 1, 2007 -- Expanding its family of synchronous Ethernet timing devices, Zarlink Semiconductor Inc. (search for Zarlink) has launched a new single-chip Gigabit Ethernet (GbE) line card synchronizer for delivery of time-critical applications over packet-based networks.
The ZL30107 chip, which is in volume production now, provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures. Integrating independent analog and digital phase-locked loops (PLLs), the device synchronizes with standard telecom and Ethernet clocks and generates an IEEE 802.3 jitter-compliant 25-MHz GbE output clock.
"Synchronous Ethernet is a key technology as service providers aggressively seek new ways to more efficiently support time-sensitive applications over packet networks," says Darren Ladouceur, marketing manager, timing and synchronization, Zarlink Semiconductor. "Building on our established synchronous Ethernet timing solutions, the ZL30107 chip allows manufacturers to easily build timing capabilities into next-generation networking equipment."
Currently, service providers must operate a number of different networks and deploy costly external mechanisms to support legacy services over IP architectures. For example, network synchronization between remote multiservice access platforms are connected to central office equipment via T1/E1 or SONET/SDH links.
In comparison, synchronous Ethernet technology allows service providers to deliver all services over a single converged, high-bandwidth, synchronous Ethernet link.
The ZL30107 device supports synchronous, holdover, and asynchronous free-run modes of operation. In synchronous operation, the PLL replaces the free-running reference clock usually provided by an oscillator with a network timing reference. The device accepts three references and performs hitless reference switching. The integrated DPLL automatically synchronizes to one of a predefined set of standard telecom frequencies ranging from 2 kHz to 77.76 MHz in addition to 25 MHz.
When all references fail, the device automatically enters holdover mode and continues to generate an output clock based on frequency data collected from past reference signals.
The chip defaults to asynchronous free-run mode, where the DPLL generates an output clock with frequency accuracy equal to an external oscillator or low-cost crystal. The company claims this allows equipment manufacturers to "build-in" synchronous Ethernet capabilities in next-generation networking equipment, allowing service providers to easily enable synchronous Ethernet capability when it is required.
Zarlink and Marvell recently demonstrated synchronization over the Ethernet physical layer using their respective PLL and Ethernet PHY technologies. An application note outlining Zarlink-Marvell interoperability is available online at http://assets.zarlink.com/AN/ZLAN_211_AppNote_Jan07.pdf.