EZchip introduces first members of its NP-2 network processor family
March 15, 2004 San Jose, CA--EZchip Technologies, a subsidiary of LanOptics Ltd., is disclosing details of its NP-2 family of network processors. The first two models of the NP-2 family consist of NP-2s, a 10-Gigabit Ethernet/SONET/SDH device, and NP-2e, a 10-Gigabit Ethernet-only device.
March 15, 2004 San Jose, CA--EZchip Technologies, a subsidiary of LanOptics Ltd., is disclosing details of its NP-2 family of network processors. The first two models of the NP-2 family consist of NP-2s, a 10-Gigabit Ethernet/SONET/SDH device, and NP-2e, a 10-Gigabit Ethernet-only device. Both NP-2 devices integrate a 10-Gbit/sec duplex network processor (NPU), classification engines, two traffic managers, ten 1-Gbit/sec media access controllers (MACs) and one 10-Gbit/sec MAC in a single chip. The NP-2s also features two SPI4.2 interfaces with up to 192 channels.
Sampling for both NP-2 devices is slated for the fourth quarter of 2004, using TSMC 0.13 micron process. The NP-2s is priced at $795 and the NP-2e at $595 in quantities. NP-2 is based on the proven architecture of the now in production NP-1c, uses the same simple programming model and is software compatible to the NP-1c. A previously announced model of the NP-2, integrating TCP offload and security engines to address the services market, is expected to sample next year. Additional NP-2 models targeting both lower and higher speeds than 10 Gbits/sec as well as other market segments will be announced separately.
"The NP-2 builds on the success of the NP-1c while reducing system chip count, cost, and power," noted Linley Gwennap, principal analyst of The Linley Group. "The NP-2 is the first announced chip to combine a network processor and traffic manager for full-duplex 10-Gbit/sec applications. It enables a lower system cost and far lower system power than any 10-Gbit/sec NPU available today."
"EZchip continues its thrust forward to lead the network processors market," said Eli Fruchter, president and chief executive of EZchip. "NP-2 solidifies our 10-Gbit/sec NPU leadership established with the NP-1c by furthering the integration and reducing the system chip count, power, and cost. The NP-2s and NP-2e are first in a family of highly integrated network processors that will address more market segments and more speeds. By integrating all of the key line card components into a single chip, the NP-2 addresses a wide range of networking applications in the wide area network, metro area network, and data center. Specifically in the cost-sensitive metro segment, the NP-2 can win over other network processors with its unmatched integration and over non-programmable network ASICs with the unlimited flexibility it provides."
The NP-2 is a highly integrated network processor family featuring 10-Gbit/sec full-duplex processing in a single-chip. The NP-2 integrates several functions that would normally be found in separate chips: 7-Layer 10-Gbit/sec duplex processing, classification search engines, two traffic managers for ingress and egress traffic management, ten 1-Gbit/sec and one 10-Gbit/sec Ethernet MACs and two duplex SPI4.2 interfaces. The NP-2 uses commodity DRAM for all its lookup tables, frame memory, and traffic management control to minimize system cost and power dissipation. For maximum flexibility a choice of DRAM technologies are supported: SDRAM DDR-II, FCRAM-II and RLDRAM-II.
Integrated classification search engines eliminate the need for expensive and power-hungry CAMs or even SRAMs. All types of look-up and classification tables are stored in low-cost low-power DRAM and provide large headroom for application scaling. Two traffic managers provide advanced quality of service by supporting DiffServ and IntServ services and a wide variety of mechanisms including: per-flow metering, policing and shaping, WRED congestion avoidance, as well as priority or WFQ hierarchical scheduling. For accurate bandwidth control, a separate traffic manager is provided for both the ingress and egress traffic flows enabling traffic shaping and scheduling after processing has been completed, and prior to transmission to the network ports or switch fabric. Each of the traffic managers with its associated memory chips can be bypassed in applications that use external traffic managers.
The on-chip MACs provide direct connection to ten 1-Gbit/sec and one 10-Gbit/sec Ethernet ports eliminating the need for external MACs. The two SPI4.2 interfaces can bypass the integrated MACs and provide flexibility to connect to switch fabrics and Ethernet or SONET/SDH framers. Up to 192 channels are available supporting virtual concatenation and hitless bandwidth allocation through the link capacity adjustment scheme (LCAS).
The NP-2s with Ethernet and SPI4.2 interfaces and NP-2e with Ethernet-only interfaces will sample in the fourth quarter of 2004. Other NP-2 models targeting lower and higher speeds than 10-Gigabit as well as other market segments will be announced separately.