Fujitsu develops ultra-low-power transceiver chipset
February 18, 2004 Kawasaki, Japan-- Fujitsu Laboratories Ltd. announced the development of a new communications chipset that uses Indium Phosphide-based high-electron mobility transistor (InP-HEMT)technology to enable 50-Gbit/sec operation of a 4:1 multiplexer and 1:4 demultiplexer chipset.
February 18, 2004 Kawasaki, Japan-- Fujitsu Laboratories Ltd. announced the development of a communications chipset that uses Indium Phosphide-based high-electron mobility transistor (InP-HEMT)technology to enable 50-Gbit/sec operation of a 4:1 multiplexer and 1:4 demultiplexer chipset. The company claims the chipset is the first to achieve superior signal quality and operating margins in full-rate clocking scheme, with breakthrough low-power consumption of less than 1 watt (70% lower than conventional technology).
The technology was developed to deliver 40 Gbits/sec throughput levels required of chips for next-generation telecommunications. Details of this technology are being presented at the 2004 IEEE International Solid-State Circuit Conference, being held in San Francisco from February 15.
There is a worldwide push to develop new terabit-class optical communications systems that will dramatically raise existing data transmission capacity by 10 to 100 times. To enable such achievements, WDM, which multiplexes multiple 40-Gbit/sec optical signals is recognized as an effective method.
Since WDM requires a quantity of electrical signal-processing circuits equivalent to the number of optical signals that are multiplexed together, as the level of multiplexing increases, so does the overall system's power consumption. As such, there is strong demand for power consumption reduction of the electrical signal-processing circuits that comprise the system.
Thus far, the reduction of power consumption without degrading superior signal quality and operating margins had been a daunting issue to overcome for multiplexers and demultiplexers that process high-speed signals as much as 40 Gbits/sec.
Fujitsu's new technology has the following key features:
Multi-phase clock technology. New circuit architecture was developed in which the circuit internally generates clock signals with different phases and utilizes them to process data signals. This new architecture ensures superior signal quality without the need for a phase-control circuit. By eliminating the phase-control circuit that required by conventional circuits, Fujitsu succeeded in significantly reducing power consumption.
Optimized voltage distribution. Through innovative optimized voltage distribution design focused on transistor size and transistor logic operation, Fujitsu was able to reduce supply voltage to less than half (1.5 volts) the voltage that was conventionally required.
InP-HEMT technology. By incorporating InP-HEMT technology, ideal for high-speed performance, full-rate clocking mode was utilized to enable superior signal quality and operating margins. This makes it possible to sync the circuit on the clock signal's trailing edge only, resulting in improved quality of multiplexer output signals and higher demultiplexer operating margins.
The new technology succeeds in delivering high speeds and superior signal quality while benefiting from low power consumption that is expected of CMOS technology. The chipset operates on power consumption of less than 1 watt, while enabling 50 Gbits/sec of throughput, more than adequate for 40-Gbit/sec systems.
According to the company, the 4:1 multiplexer attains the world's highest quality signal in terms of jitter - 284 femtoseconds (femto=one-quadrillionth) - and the 1:4 demultiplexer achieves a clock phase margin of 250 degrees. By using the newly developed chipset in 40-Gbit/sec optical communications systems, significant reduction of overall system power consumption is anticipated.
Fujitsu plans to leverage this technology to develop circuits such as 16:1 multiplexers and 1:16 demultiplexers that work with 2.5-Gbit/sec interface, a candidate for system standardization, to offer greater performance and higher levels of integration for terabit-class communication systems.