Agilent launches next-gen Tachyon DX2 Fibre Channel controller IC
12 August 2003 BÃ¶blingen, Germany Lightwave Europe -- Agilent Technologies has introduced its latest Tachyon DX2 Fibre Channel controller IC. The fourth-generation HPFC-5400D Tachyon controller IC is designed for mid- to high-end storage applications.
12 August 2003 BÃ¶blingen, Germany -- Agilent Technologies has introduced its latest Tachyon DX2 Fibre Channel controller IC. The fourth-generation HPFC-5400D Tachyon controller IC is designed for mid- to high-end storage applications.
One Tachyon DX2 chip supports dual-channel, full duplex Fibre Channel port operation, which saves valuable board space for system manufacturers, while providing backward compatibility to previous generation Tachyon controllers.
The company says that storage area network solution providers are seeking higher bandwidth, greater connectivity, lower cost per port, higher integration and lower manufacturing costs, while conserving PCI slots within their servers.
Agilent adds that its 2-Gbit/s Tachyon DX2 Fibre Channel Controller meets these requirements, making it suitable for embedded subsystems, disk arrays, SCSI to Fibre Channel bridges and host adapters.
The HPFC-5400D is a single-chip, dual-channel Fibre Channel controller solution that offers full duplex capability within each channel and provides both 2-Gbit/s and 1-Gbit/s operation.
It interfaces to the industry standard 33 and 66-MHz PCI (Peripheral Component Interconnection) and 66/100/133 MHz PCI-X (enhanced PCI) bus architecture with 32- and 64-bit support. The Tachyon DX2 chip also includes integrated SerDes, which in other solutions must be implemented with a separate device. It also allows for an external HSPI-compatible 10-bit SerDes.
Agilent's state machine architecture scales proportionately with system CPU resources to avoid performance bottlenecks associated with on-chip processors. The Tachyon architecture allows for simultaneous, parallel processing of inbound data, outbound data, and hardware control and commands to maximize bandwidth and minimize latency and I/O overhead.