APRIL 11, 2008 -- TPACK (search for TPACK) has introduced a new SOFTSILICON product, the SMARTPACK TPX3103 52-Gbit/sec Carrier Packet Engine. The TPX3103 is an upgraded version of the TPX3100 PBB-TE/T-MPLS/VPLS Carrier Packet Engine, the first commercial chip to offer support for all of these protocols simultaneously.
The TPX3103 is based on an Altera Stratix III FPGA, with a power consumption of 12 W per device. Based on a mated device configuration, the TPX3103 can provide a maximum non-blocking, full-duplex switching capacity of 52-Gbits/sec allowing a maximum of 48x 1-Gigabit or 4x 10-Gigabit Ethernet ports. As a SOFTSILICON product, it is offered as a standard chip similar to an ASSP, but is designed to enable rapid updates in response to changes in PBB-TE, T-MPLS, and VPLS standards.
"Due to the number of new concepts continually introduced in the emerging Carrier Ethernet segment, such as PBT (PBB-TE) and T-MPLS, OEMs are unsure which concepts will become the de facto standard for supporting Carrier Ethernet services," said Aileen Arcilla, principal analyst at IDC. "Unlike NPUs and network processing ASSPs, offering a FPGA-based solution can allow OEMs to address the flexibility in support and time-to-market issues associated with rapid changes in Carrier Ethernet requirements."
Particularly well suited for Carrier Ethernet gateway devices, according to TPACK, the TPX3103 is designed to provide full hardware support for PBB-TE and T-MPLS OAM, allowing protection switching times well within the 50-msec carrier-grade specification.
In addition, the TPX3103 offers extended security control with Access Control Lists, more RMON monitoring capabilities, and enhanced ingress flow control mechanisms, which also makes the TPX3103 suitable for application in a number of platforms including Carrier Ethernet switches, MSPPs and packet optical transport platforms, TPACK concludes.
The TPX3103 is now available.