July 10, 2006 Santa Clara, CA -- Enigma Semiconductor today announced it is sampling what it claims is the world's first linearly scalable packet switching chipset. Based on the company's HybriCore architecture, the chipset streamlines time-to-market for OEMs designing next-generation metro access switches and routers, multi-service provisioning platforms (MSPPs), enterprise routers, and storage platforms, say company representatives.
According to the company, its chipset family, which features both packet switches and a range of fabric managers, sets new benchmarks for density, efficiency, and flexibility.
Traditional shared-memory architectures offer limited system scalability, while existing cell-based architectures are inherently inefficient. The HybriCore memory-less crossbar switches announced today uniquely address both of these challenges, scaling to support multiple-terabit configurations and switching complete packets across the backplane to eliminate segmentation and reassembly, says the company. This scalability and efficiency allows system architects to future-proof their network and communications systems by ensuring that next-generation line cards can be deployed within existing hardware infrastructure platforms.
"With rising demands from both enterprise and carrier network providers, the only way to achieve the next level of switching scalability is to break the mold," contends Rob Sturgill, president and CEO of Enigma Semiconductor. "Finally, with the release of the HybriCore chipset, system architects have a fully scalable packet-based switching system for building elegant and robust carrier and enterprise equipment to support triple-play applications. These silicon building blocks support user-defined quality-of-service levels, ultimately ensuring a positive user experience with these value-added, revenue-generating services."
Enigma's HybriCore chipset family initially includes two packet switches and three fabric managers. These devices can be mixed and matched to allow system architects to make tradeoffs based on system power, performance, and cost requirements. The EN6105 integrated switch is optimized for use in small modular chassis or "pizza box" applications that demand minimal footprint, low power, and low cost. The EN6110 is designed to address massively scalable network equipment architectures, with the capability to directly address up to 36 line cards.
The EN6210 Fabric Manager is a 10-Gbit/sec single-chip line card solution, the EN6220 Fabric Manager is a 20-Gbit/sec single-chip line card solution, and the EN6240 is a 40- Gbit/sec single-chip line card solution. No external buffer memory is required in designs based on these fabric managers, which minimizes power dissipation and PCB footprint. The EN6200-family of fabric managers incorporates industry-standard interfaces for direct connectivity to a range of network processor units (NPUs), ASICs, and specialty packet processing devices.
Density
A single HybriCore-based switch device switches up to 360 Gbits/sec of non-blocking, full duplex traffic. Multiple switch devices scale the design linearly to support multiple terabit system configurations that have not been possible with legacy switching silicon. The fabric managers, residing on the line card in a typical system topology, support 10-, 20-, or 40-Gbit/sec line card configurations and can be combined to achieve higher density 80-, 120-, and 160-Gbit/sec implementations. This device requires no external buffer memory, which reduces PCB footprint, system power, and system cost.
Efficiency
Legacy switch architectures typically convert packets into equal-length cells, forcing a significant amount of backplane bandwidth to be used for cell headers-and, in some cases, for partially empty cells. Maintaining scalability with this legacy approach requires a substantial increase in aggregate bandwidth across the backplane, increasing design complexity, power, and cost.
The HybriCore chipset achieves performance and scalability by switching complete packets across the backplane without the inefficiencies introduced by segmentation and reassembly schemes typical of legacy switching architectures, notes the company. An intelligent scheduler ensures packets are transferred back-to-back across the serial links, resulting in bandwidth utilization of greater than 98%. The scheduler also ensures high priority packets are switched with very low latency, even when the switch is concurrently transporting large packets.
Flexibility
Enigma has incorporated enhanced ABP (Advanced Backplane) technology from Rambus into the HybriCore chips to provide robust serial links that support data rates from 2.5 Gbits/sec through 12.5 Gbits/sec. These serial links integrate sophisticated equalization schemes to ensure reliable operation despite changes in temperature, voltage, and humidity. The family of HybriCore chips supports a range of performance and price targets, providing design flexibility for system architects.
Moreover, Enigma claims it delivers carrier-class network reliability with HybriCore's intelligent backplane links, which integrate multiple feedback loops and control paths. The chipset is designed so that systems can use one of many available redundancy schemes to deliver reliable failover mechanisms and maintain the highest performance and reliability standards. This ensures the system will operate reliably over long periods of time, regardless of environmental changes.
All devices are available for sampling now.