Xelerated has unveiled the HX336 network processor, which features integrated traffic management. When paired in the egress path with the previously announced HX326 network processor in the ingress path, designers can replace as many as six chips in 100 Gigabit Ethernet and OTU4 designs with two, according to Per Lembre, Xelerated’s director of product marketing.
The network processor combination not only leads to more streamlined designs in Carrier Ethernet switch/router and packet-optical transport system applications, but power consumption savings as well, Lembre asserted in an interview with Lightwave. A six-chip design would require more than 200 W, Lembre said; use of the new HX336 and the HX326 network processors would reduce that power requirement to around 100 W. The HX336 itself obviates the need for separate packet processor, traffic manager, and buffer manager devices, Lembre added.
The HX336 network processor leverages Xelerated’s dataflow architecture to perform 100 Gbps packet processing at wire speed. The integrated traffic manager only requires DRAM as external packet buffer memory.
Other features Xelerated highlights include:
- 100-Gbps and 150-Mpps buffering, shaping, and scheduling
- Guaranteed wire-speed performance for all packet sizes
- Flexibly configurable hierarchical scheduler that enables all bandwidth to be assigned to a single 100GE/OTU4 port
- Flexibly configurable backpressure from ports or fabric devices
- An architecture that linearly scales with industry DRAM evolution.
”System vendors are facing significant power budget restrictions when moving from 10 Gigabit Ethernet [GE] to 40GE and 100GE solutions," said Bob Wheeler, senior analyst at The Linley Group. “Continued innovation in optics, packet processing, and buffering will be required to make 100GE commercially successful. Xelerated’s unique design is an example of an NPU which is addressing the very root of the problem.”
The HX336 will sample in August 2011, Lembre concluded.
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