SEPTEMBER 30, 2009 -- Xelerated, a supplier of Carrier Ethernet and unified fiber access ASSP-based chipsets, has launched the latest release of its software development kit (SDK), the SDK 5.0. Designed to support Xelerated's new generation of HX Carrier Ethernet network processors (NPUs) and AX programmable Ethernet switches, SDK 5.0 has been developed to optimize network design for next-generation Carrier Ethernet platforms and devices.
Now shipping to customers, the SDK 5.0 supports all device types of the two families, allowing system vendors to seamlessly develop and customize data plane software for their unified fiber access and next-generation metro Ethernet platforms, says Xelerated. The instruction set and programming model are compatible with previous NPU generations, easing re-use of existing applications and migration of code for existing X11 customers who are looking to optimize their data planes with the capabilities of new-generation Carrier Ethernet devices.
The SDK 5.0 provides a range of software development tools:
integrated development environment (IDE), where programmers can access all tools for code editing, compilation, simulation, and debugging
analyzer tool with an intuitive overview of how instruction memory is utilized
simulation and debugger tools for step-by-step validation of any packet type
"At Xelerated, we want our customers to have the right tools available to make the most out of the new Carrier Ethernet devices," says Fredrik Orava, vice president of software at Xelerated. "With the SDK 5.0, vendors can jumpstart their design processes for the new generation of unified fiber access and metro Ethernet products that service providers are demanding. We look forward to seeing how these projects unfold and how platforms are being developed for the next level of packet processing capabilities, intelligent aggregation, and superior integration."
As with previous-generation NPUs by Xelerated, the HX and AX Carrier Ethernet devices leverage data flow architecture, with a deterministic pipeline of processor cores. A processor's code can be written with a single instruction set using a straightforward sequential programming model. Once the code is successfully compiled, wirespeed performance is guaranteed for all packet sizes and services. The homogenous pipeline of processor cores simplifies code adoption for systemization of advanced and evolving unified fiber access and metro Ethernet requirements.