FEBRUARY 10, 2009 -- Sierra Monolithics has unveiled its fourth-generation 40G multiplexer with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR). The devices are designed to incorporate all required pre-coding circuitry for long-reach applications and superior signal integrity, and uses IBM's 8HP silicon germanium (SiGe) bipolar complementary metal oxide semiconductor (BiCMOS) process technology to achieve significant power reductions versus previous SerDes product generations.
The latest 130-nm generation of IBM's SiGe process doubles the performance of previous generations and also improves power efficiency and integration. These process advances enable the SMI4027 to support a range of data rates from 39.8 to 44.6 Gbps while simultaneously incorporating an on-chip, user-enabled differential phase shift keying (DPSK) precoder function.
"In our 10/40/100G market study released last October, Infonetics reported that, despite the economic downturn, 40G was ramping rapidly, and 100G should begin soon and take off by 2013," said principal analyst and co-founder of Infonetics, Michael Howard. "These technologies are critical for alleviating the tremendous strain due to data center growth and consolidation, and video applications on business, consumer broadband, and mobile networks. Components in the supply chain such as these new 40G mux and demux devices from Sierra Monolithics will play a key role in helping to ensure that growing traffic demands don't outstrip network capacities. We expect 40G revenue to increase at a compound annual growth rate (CAGR) of 59 percent from 2007 to 2011."
The SMI4027 and SMI4037 devices are designed to enable all common modulation formats in the 39.8-Gbps to 44.6-Gbps data range. They also incorporate a fully SFI-5-compliant client-side interface. Other features include ground-referenced high-speed differential output ports, high-speed differential clock outputs with low phase noise, and a SONET-compliant CMU with on-chip voltage controlled oscillator (VCO). Additionally, the devices include two user-selectable reference clock input ports and reference clock clean-up loop circuitry.
Rounding out the feature set for the mux are a phase detector on-chip dual-mode (PRWS) error checker and pattern generator, a 512-bit arbitrary pattern generator, and an SPI control interface the supports a wide range of logic families. The SMI4037 demux has CDR and SONET-compliant clock jitter tolerance. The devices operate from dual-power supply voltages of +1.2 V or +1.8 V and -2.8 V, a combined power consumption of just over 4 W typical (with high-speed clock outputs disabled) for the chipset.
The SMI4027 and SMI4037 devices are sampling now and scheduled to enter volume production in the second quarter of 2009. They are packaged in a ball grid array (BGA) with GPPO connectors.
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