Cortina touts low latency of new CS4315 EDC chip
MARCH 15, 2010 By Stephen Hardy -- Cortina Systems Inc. has unveiled the CS4315, its second-generation electronic dispersion compensation (EDC) device for 10-Gigabit Ethernet (10GbE) applications (see "Cortina Systems intros EDC family" for information on the first generation). The chip offers low latency and power consumption with the flexibility to be used in a variety of SFP+ and backplane applications, says a company source.
The dual-port/quad-CDR PHY and EDC device can support SFP+ 10GBase-SR/LR/LRM and direct-attach copper cable as well as backplane applications, says Scott Feller, product line director at Cortina. Both transmit and receive paths include CDR circuits. The analog-based chip can be programmed to enable designers to optimize performance versus power consumption, he adds. Depending upon the application, power consumption might range from 180 mV to 750 mV, Feller says. The adjustable pre-emphasis and equalization can support trace lengths of 8 to 16 inches, he adds.
The CS3415 also offers a latency of less than 1 ns, which Feller contrasts with what he says is a typical latency figure of greater than 80 ns for competing chips.
The device’s operating frequency range enables its use in such diverse applications as GbE and 10GbE, 1G/2G/4G/8G Fibre Channel, and SONET (9.5 to 11.3G). Feller says the company has a design win for a SONET application.
The chip is already in production and shipping in volume, according to Feller. “We’re doing very well volume-wise,” he says.
Visit Cortina Systems