Fujitsu Microelectronics Europe, Vectron International tout 100G coherent receiver analog reference design

MARCH 3, 2010 -- Fujitsu Microelectronics Europe (FME) and Vectron International say they will demonstrate Fujitsu's CHArge-Interleaved Sampler (CHAIS) ADC technology with the Batboard evaluation platform at the annual OFC/NFOEC in San Diego, March 23-25, 2010.

MARCH 3, 2010 -- Fujitsu Microelectronics Europe (FME) and Vectron International say they will demonstrate Fujitsu's CHArge-Interleaved Sampler (CHAIS) ADC technology (see "Fujitsu launches ADC technology for 100G") with the Batboard evaluation platform at the annual OFC/NFOEC in San Diego, March 23-25, 2010. The ADC reference clock will be driven by Vectron's VS-401 VCSO.

"Vectron's innovation and leadership in SAW oscillator technology allows us to meet the ever-increasing performance demands of the next-generation networks operating at 100 Gbps and beyond," said Ben Witham, product line manager, Vectron. "Fujitsu chose the VS-401 for this demonstration at OFC because it is uniquely suited to deliver the extremely high performance necessary for the company's ADC technology."

"We are pleased to be collaborating with Vectron International to demonstrate real-world ADC and VCSO performance at these frequencies," said Neil Amos, communications business unit director, FME. "Vectron's technology offering for ultra-low jitter reference clock sources is complementary to Fujitsu's CHAIS ADC program, both developments serving as key enablers for 100G coherent receiver designs."

FME's second generation 8-bit CHAIS ADC for 100-Gbps coherent receiver designs supports data rates up to 63 GSa/s. Based on the same ADC architecture as Fujitsu's 56-GSa/s CHAIS ADC (see "Fujitsu offers 56-GSa/sec ADC evaluation kit"), the new design will again offer the ultra-fast sampling rates, wideband input, low noise, and high resolution required for optical data transport at 100-Gbps over long-haul and ultra long-haul links, FME asserts.

Implemented in 40-nm CMOS technology, the 63-GSa/s CHAIS ADC will surpass the low-power performance of the first generation and will support higher FEC overheads for longer reach, FME adds. The fundamentals of the CHAIS architecture support scalability to higher sampling rates for future transport data rates (400 Gbps/1 Tbps) and power dissipation that scales with smaller process feature size, the company concludes.

Designed primarily for 100G optical applications, Vectron's VS-401 VCSO operates at 1.747 GHz with a control voltage range of 0.5 to 4.5 V. The key feature of the VCSO is its low output jitter of 8 fs-rms (12 kHz to 20 MHz), which is well below the 100G reference clock specification, Vectron says. Housed in a 13x20-mm SMD package, the VS-401 runs off of a single +5-V supply and provides a sinusoidal output of +8 dBm typical. Initially frequencies being supported are centered around 1.747 GHz plus or minus 5% with plans to support a VCSO at 2 GHz by Q3 2010.

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