Fujitsu launches second-gen 65-GSa/s 8-Bit ADC for 100G optical transport

Sept. 13, 2010
SEPTEMBER 13, 2010 -- Fujitsu Semiconductor Europe has announced its second-generation 8-bit CHArge-mode Interleaved Sampler (CHAIS) analog-to-digital converter (ADC) for optical transport designs based on coherent detection.

SEPTEMBER 13, 2010 -- Fujitsu Semiconductor Europe has announced its second-generation 8-bit CHArge-mode Interleaved Sampler (CHAIS) analog-to-digital converter (ADC) for optical transport designs based on coherent detection. The new ADC supports data rates from 55 to 65 GSa/s and is based on the same ADC architecture as Fujitsu’s 56-GSa/s CHAIS ADC in 65 nm. It is designed to offer the fast sampling rates, wideband input, low noise, and high resolution required for long-haul links with data rates of 100 Gbps and higher over a single wavelength.

Implemented in a 0.9-V 40-nm CMOS technology, the 65-GSa/s CHAIS ADC surpasses the low-power performance of the first generation and will support higher FEC overheads for longer reach, Fujitsu Semiconductor Europe asserts. The fundamentals of the CHAIS architecture allow for scalability to even higher sampling rates for future transport data rates (400 Gbps/1 Tbps) and power dissipation that scales with smaller process feature size, the company adds. Typical power dissipation for a single CHAIS ADC channel in 40 nm is 1.2 W, down 50% from the power per channel in 65 nm.

“Fujitsu is pleased to continue to offer leading-edge ADC performance to system vendors bringing higher transport speeds to core networks”, said Neil Amos, director of the Communications Business Unit at Fujitsu Semiconductor Europe. “In addition to providing lower power solutions, scaling our ADC technology to smaller process nodes enables greater functionality in the DSP and a roadmap for smaller form factors for optical module designs”.

Fujitsu says its four-channel CMOS design enables more efficient integration with coherent receiver digital cores, typically comprising tens of millions of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. For the design of single-die transceiver SoCs in 40n m, the Fujitsu IP offering includes 11-Gbps SerDes, supporting a range of protocols and data rates, and will also include a complementary 55- to 65-GSa/s 8-bit DAC.

The package design leverages patented techniques for thermal management and noise isolation. “Integrating high-performance, very low jitter analog IP with a large, high-current spiking DSP requires careful attention to signal routing and isolation of noise-sensitive circuits,” explained Ian Dedic, chief engineer of Fujitsu’s Communications Business Unit. “Fujitsu’s experience in tackling many of the issues facing system and module developers for this type of complex SoC helps to solve real-world deployment issues”.

Fujitsu Semiconductor Europe will demonstrate the 65-GSa/s CHAIS performance at the European Conference on Optical Communications (ECOC) in Turin, Italy later this month. As with the previous generation CHAIS ADC technology, a development kit for the 65-GSa/s ADC will be available in January 2011 for customers to evaluate their modulation and FEC algorithm performance using silicon based on field-proven architectures.

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