64-channel selector beats scaling problem


Integration of WDM channel selectors should be significantly simpler now that it an optical gate isn't needed for each channel. A new two-stage device in development at NTT Photonics Laboratories in Kanagawa, Japan, requires only 2÷N gates per channel. This, researchers say, gives them a significant advantage: teams working with conventional, monolithic arrayed waveguide grating (AWG)-based devices have, as yet, only succeeded in building 16-channel selectors. In testing using a 10-Gbit/s non-return-to-zero (NRZ) signal, error-free operation was achieved with an average sensitivity penalty of just 1.3 dB.

Apart from the two-stage concept, the configuration is identical in operation to an ordinary AWG-based channel selector (see figure). The first grating separates the 64 channels into eight sets of every eighth channel, and eight semiconductor optical amplifiers (SOAs) acting as switches are used to select among these sets.1 The second AWG spaces out the chosen eight channels further, allowing one to be selected by the second set of SOAs. A multimode interference (MMI) coupler is used to recombine the light paths after selection is complete, and the signal is finally boosted before leaving the chip.

In their demonstrator, the researchers achieved a channel spacing of 50.4 GHz (50-GHz design) with a standard deviation of 4.5 GHz. All but two of the 64 channels were lossless, with a maximum loss of 1.2 dB on the others. The most serious crosstalk came from the channel adjacent to that selected, but signal was also detected from the other channels in the set that had got through the first stage. Nevertheless, researchers say, the typical crosstalk was less than –25 dB.

To characterize bit-error rate (BER), the 10-Gbit/s signal was detected with a BER of 10–9. To maintain this level of accuracy, a sensitivity penalty of 0.4 to 2.1 dB was necessary, with the input power of each channel 2.5 dBm. Switching times were found to be fast, say researchers: less than 1.5 and 1.0 ns for the rise and fall times respectively. Finally, the current injected into the SOAs (including the booster) was 65 to 167 mA.

For more information, contact N. Kikuchi at kikuchy@aecl.ntt.co.jp.

Sunny Bains

  1. N. Kikuchi et al., Elect. Lett. 38 (7), 331 (March 28, 2002).
  2. N. Kikuchi et al., Elect. Lett. 38 (15), 823 (July, 18 2002).
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