Faraday intros 28-nm 28G programmable SerDes IP for networking ASICs
The company expects the SerDes capability to find use in 100 Gigabit Ethernet and PON equipment designs.
Taiwan’s Faraday Technology Corp. (TWSE: 3035) has introduced a 28-Gbps programmable SerDes PHY IP on UMC 28HPC process technology. The company expects the SerDes capability to find use in 100 Gigabit Ethernet and PON equipment designs.
Faraday asserts the programmable SerDes IP can optimize system-on-chip (SoC) designs with 100 Gbps of throughput. The IP supports several interface standard protocols, including:
- OIF-CEI-28G VSR/SR and OIF-CEI-25G LR
- PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
- 25G to 100G Ethernet: 25G/50G/100G-KR4 and CR4
- JESD204B/C for high-speed ADC/DAC and FPGA interface.
The SerDes IP also can be used to support a variety of PON implementations, including symmetrical and asymmetrical GPON and 10GPON as well as symmetrical EPON and 10G-EPON
“28G SerDes PHY technology has become a crucial building block in addressing a broad range of wired and wireless communication applications,” said Flash Lin, Faraday’s COO. “Faraday's latest 28-nm SerDes solution can meet 25/28G SerDes requirements with lower NRE [non-recurring engineering] expense and lower cost compared with other FinFET-based 28G SerDes solutions. By leveraging this solution, we are ready to engage with ASIC customers to reach their potential needs in high-growth networking markets.”
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