Orthogone Technologies offers Ethernet MAC and PCS IP cores
Montreal-based Orthogone Technologies, which provides semiconductor intellectual property (IP) and electronic product design services, now offers Ethernet MAC and PCS IP Core products for use on FPGAs, ASICs, and ASSPs.
Orthogone says this first release offers high performance as measured by resource use, gate count, and latency. It focuses on 1-, 10-, 25-, 40- and 100-Gbps Ethernet MAC and PCS requirements for a variety of applications, including low-latency switches, packet processing based on quality of service (QoS), test and monitoring equipment, as well as other systems targeted for such popular markets as data centers and high-frequency trading.
Orthogone says the IP cores offer the following salient features and benefits:
- 10X improvement in gate count and resource use
- 38.4-ns round-trip latency for MAC and PCS at 10 Gbps in a 28-nm FPGA platform, lowest speed grade
- unified code that supports the multiple data rates mentioned above
- full integration
- timing margin of greater than 20% on mid-speed grade FPGA devices
- what the company describes as an "ultra-low gate count" channelized multi-port 1G/10G MAC option (2, 4, 8, 16 ports)
- scalability and flexibility, as the same code and documentation are valid for all rates
- a fully configurable statistics vector and collector on MAC and PCS.
The cores are designed to be plug-and-play and support FPGA devices from Altera and Xilinx as well as use in ASIC and ASSP implementations. They are provided currently under Orthogone's early access program and will be fully supported and released to the open market in Q1 2016.
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