September 10, 2002 -- Multilink Technology, a provider of advanced semiconductor-based solutions that accelerate the deployment of high-speed optical networks, today introduced their next generation, 10-Gbit/sec, Enhanced Forward Error Correction (EFEC), digital wrapper processor device; the MTC6134. This single chip, bi-directional transport device features full SONET/SDH section and line overhead processing, 10-Gbit/sec Ethernet performance monitoring and G.709 digital wrapper termination and generation for 10-Gbit/sec systems. The EFEC advantage provides metro applications with over 8.5 dB of net coding gain at 1x10 -15 corrected bit error rate, based on a successful approach used by the MTC6131 SuperFEC, and only 3.5 watts of power dissipation.
The MTC6134 FEC device provides error correction of arbitrary data streams of 10 Gbits/sec in data and telecom networks and can significantly extend the reach of metro optical systems. Error correction is provided based on a block oriented Reed-Solomon code RS (255,239) in addition to an optional proprietary FEC code that provides increased net coding gain with the same 7% overhead. Integrated overhead processing makes it especially suitable for OC-192/STM-64 SONET/SDH and 10-Gbit/sec Ethernet transport applications. The device also supports single chip RS FEC to EFEC bridging and RS FEC to RS FEC regeneration.
The device also includes integrated 10 Gigabit Ethernet physical coding sublayer/media access control blocks for performance monitoring, support for a proprietary communications channel, comprehensive FEC statistics with dedicated error signal outputs and optimized package I/O.
Customers can interface the MTC6134 with Multilink's physical layer devices to have a full linecard solution for metro applications. The MTC6134 will be available during the fourth quarter of 2002 in an 896-pin ceramic ball and grid array package (35 x 35 mm). It is priced at $750.00 for sample quantities.