Communications IC vendor MoSys (NASDAQ: MOSY) says it has begun sampling its MSR620 Bandwidth Engine 2 – Burst chip, which the company asserts offers the highest bandwidth density and highest access rate of any single-chip option. Targeted at such applications as networking routing and switching line cards with aggregate rates of 100 Gbps and above, the device reduces the risk of dropped packets in the data path caused by extended distances, oversubscription, mismatches in data rates, or real time processing, MoSys asserts.
The MSR620 interface uses sixteen 15-Gbps SerDes lanes to operate at 480 Gbps and provides the host with up to 384 Gbps CRC protected, effective data throughput. This represents an 80% overall efficiency, MoSys says, which places it beyond the capability of standard memory subsystems and alternative serial interface approaches. An MSR620 device can support up to 5 ms of packet buffering for a 100G interface, smoothing transient peaks and providing the traffic manager the time necessary to process and prevent lost packets, the company says. In comparison, alternative architectures often demand complex and expensive board designs that result in more than twice the board area and power, MoSys claims.
The MSR620, the first of MoSys’s second-generation Bandwidth Engine architecture family supports optional use of MoSys's Bit Safe Self Test and Self Repair Technology, which enables in-field test and repair capabilities.
The first-generation Bandwidth Engine ICs have been fully qualified for carrier-grade applications and are available for volume production now. The company is currently accepting sample orders for the MSR620 device.
For more information on communications ICs and suppliers, visit the Lightwave Buyer’s Guide.