PMC-Sierra announces family of serializer/deserializer devices for metro transport networks
Extending its physical layer product line for high-speed optical networks, PMC-Sierra (NASDAQ: PMCS) announced the PM8355 QuadPHY-II, PM8351 OctalPHY and PM8353 QuadPHY. These highly integrated Serializer/Deserializer (SERDES) devices are designed to lower the power and speed the deployment of high density Gigabit Ethernet, Fibre Channel, Infiniband optical module interfaces, and multi-gigabit serial backplanes in next-generation optical networking equipment. The QuadPHY-II, OctalPHY and QuadPHY devices dramatically increase system design flexibility by allowing easy interconnection of chip level and board level building blocks used in Gigabit and Terabit Switches/Routers (Enterprise, Access, Edge, and Storage Area Networks) and Multi Service Provisioning Platforms.
PMC-Sierra's flagship QuadPHY-II offers what the company claims to be the industry's widest range of Gigabit serial backplane operation, from 1 Gbit/s to 3.125 Gbit/s, while supporting 10 Gigabit Ethernet, Fibre Channel and Infiniband (2.5 Gbit/s) optical applications. As a 10 Gigabit Ethernet PHY, the QuadPHY-II supports the emerging XAUI and Coarse Wavelength Division Multiplexing (CWDM) optical module serial interfaces. It also provides a standard XGMII parallel interface for seamless connection to 10Gbit/s Media Access Controllers (MACs). Its per-channel selectable half-rate mode can support either 1.06 Gbit/s or 2.12 Gbit/s Fibre Channel rates on each port independently.
The OctalPHY, an eight port SERDES, and QuadPHY, a four port SERDES, are the first multi-port gigabit SERDES devices with standard Gigabit Ethernet features such as Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), GMII (Gigabit Media Independent Interface) and auto-negotiation capabilities. Additional features include disparity correction, redundant high speed I/Os, and multi-channel lane to lane de-skew and clock synchronization. With less than 160 milliwatt power per port, PMC-Sierra claims its SERDES family offers the industry's lowest power and smallest footprint with its 19x19 mm PBGA package.
"The QuadPHY-II, which we showcased in a live 4 channel, 3.125 Gigabit loop back application generating zero receive side errors at the recent Optical Fiber Communication Conference, addresses the emerging IEEE 802.3ae XAUI 10 Gigabit Ethernet Optical Module Standard. In addition to targeting Enterprise, Metro and Core WAN markets, we have seen a great demand for our multi-port, multi-gigabit SERDES in Storage Area Networks and Server-to-Server serial backplane connectivity applications," said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division.
The multiple channels of the QuadPHY-II, OctalPHY and QuadPHY chips can be aggregated or "trunked" together to provide up to 12.5 Gbit/s of total bandwidth in each direction. When its four channels are trunked, the QuadPHY-II can effectively deliver a payload of 10 Gbit/s for emerging applications such as 10 Gigabit Ethernet transmitted over Wavelength Division Multiplexing fiber or high speed serial backplanes. Integrated FIFOs and de-skew logic ensure the proper channel to channel synchronization required for these trunking applications.
The PM8351 OctalPHY, PM8353 QuadPHY and the PM8355 QuadPHY-II are packaged in a 19-mm by 19 mm, 289 PBGA package. They are priced at $53, $39, and $80 respectively in 1KU quantities. All products are currently sampling or available in production quantities.
About PMC-Sierra:
PMC-Sierra develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1, T3/E3, Packet-over-SONET, Voice-over-Packet, wireless infrastructure, MIPS microprocessor, and Gigabit Ethernet solutions for wide area network (WAN), and Internet networking equipment. For more information, visit www.pmc-sierra.com.