Vitesse and Finisar demonstrate 10G 300-km link

FEBRUARY 29, 2008 -- The link incorporates Finisar's tunable DM200 chirp-managed laser transmitter and Vitesse's new VSC8240 clock and data recovery IC with integrated electronic dispersion compensation.

FEBRUARY 29, 2008 -- Finisar Corp. (search for Finisar)and Vitesse Semiconductor Corp. (search for Vitesse) say they have achieved a 300-km optical link at 10 Gbits/sec using standard non-return to zero (search for NRZ) modulation that does not require dispersion-compensating fiber. The link incorporates Finisar's tunable DM200 chirp-managed laser transmitter and Vitesse's new VSC8240 clock and data recovery IC with integrated electronic dispersion compensation. The demonstration is being held this week at OFC/NFOEC 2008 in San Diego, CA.

The 300-km transmission is enabled by Finisar's CML laser and Vitesse's CDR/EDC. This combination provides a low-power system (<2.5 W) that eliminates the need for dispersion-compensation modules in 10-Gbit/sec metro DWDM networks.

"The result of this collaboration enables our telecom OEM customers to design transmission equipment that will achieve a 300-km reach," claims Frank Fan, marketing director at Finisar.

The transmitter is available in a TOSA format or butterfly package and is capable of 4x100-GHz or 8x50-GHz narrow tunability across C- and L-band wavelengths. The CML uses a directly modulated, standard distributed-feedback (DFB) laser and a passive optical spectrum reshaping filter to achieve extended reach.

The VSC8240 is a low-power, CMOS-based CDR with integrated EDC functionality derived from Vitesse's line of EDC and physical layer products covering 10-Gigabit Ethernet and SONET/SDH applications for Carrier Ethernet and optical transport networks. The company says it "works well" in singlemode fiber reach extension applications.

The VSC8240 compensates for both SMF chromatic dispersion and polarization-mode dispersion in a poor OSNR environment. Utilizing a decision-feedback equalizer and feed-forward equalizer EDC architecture, it implements an integrated, self-adaptive algorithm that eliminates system adjustments.


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