ClariPhy targets metro with 40G LightSpeed Coherent SoC

Having triumphed in the coherent 40-Gbps long-haul space, ClariPhy Communications, Inc. has now turned its sights on metro and regional networks with a new version of the CL4010 LightSpeed Coherent SoC. The metro-focused version of the chip can operate at a data rate of 47 Gbps to support the forward error correction (FEC) necessary to ensure 40-Gbps transmission alongside lower-speed signals.

Having triumphed in the coherent 40-Gbps long-haul space, ClariPhy Communications, Inc. has now turned its sights on metro and regional networks with a new version of the CL4010 LightSpeed Coherent SoC. The metro-focused version of the chip can operate at a data rate of 47 Gbps to support the forward error correction (FEC) necessary to ensure 40-Gbps transmission alongside lower-speed signals.

The SoC leverages dual-polarization quadrature phase-shift keying (DP-QPSK) coherent technology. ClariPhy developed its new capabilities in collaboration with fellow semiconductor supplier Cortina Systems Inc., according to Paul Voois, co-founder and chief strategy officer at ClariPhy. The partnership derived from the need to overcome the cross-phase modulation (XPM) impairments likely to be encountered when transmitting coherent 40-Gbps signals alongside 10-Gbps wavelengths. ClariPhy leaned on Cortina’s FEC expertise in the CL4010’s design process, Voois says. As a result, ClariPhy recommends that its module and system developer customers pair its 40G coherent SoC with Cortina System’s FEC-enabled CS604x and CS600x Optical Transport Network (OTN) processors.

The combination of the ClariPhy and Cortina devices results in an optical signal-to-noise ratio (OSNR) sensitivity improvement of up to 3 dB, according to ClariPhy. This translates into the ability to transmit coherent 40-Gbps signals through up to 15 spans and a reach of at least 1200 km.

For applications that require FEC with greater than 13% overhead, ClariPhy also offers the CL5018 LightSpeed Coherent SoC. This chip, which supports data rates from 47 Gbps to 50 Gbps, is designed to be used with Cortina’s 20% and 25% overhead FEC codes.

Voois added ClariPhy has designed the device to be power- and cost-effective, but declined to provide specific figures for either parameter.

ClariPhy has shipped the original version of the CL4010 since 2011 to such module vendors as Oclaro, NEC, and JDSU (see, for example, “ClariPhy, Oclaro tout 40-Gbps coherent”). The new version of the CL4010 is production ready, Voois says; modules using the device are expected to sample this month.

It appears that Oclaro, for one, is already onboard. “The higher bit rate capability of the enhanced LightSpeed SoC from ClariPhy will help our customers to deploy 40G coherent line cards more widely in metro networks, which are already carrying intensity modulated wavelengths such as conventional 10G connections,” said Richard Smart, senior vice president and general manager of Optical Network Subsystems at Oclaro via a ClariPhy press release. “This feature enables network operators to introduce coherent technology more pervasively without having to build overlay networks.”

The announcement of the metro 40-Gbps coherent SoC comes only a few days after MultiPhy announced its intention to have a chip for coherent 100-Gbps metro applications in customers’ hands by the end of next year (see “MultiPhy details 100-Gbps metro coherent DSP transceiver plans”). Voois acknowledged that ClariPhy has a 100-Gbps coherent transceiver on its roadmap but declined to provide details, other than to say it plans to address 100-Gbps requirements in both long-haul and metro/regional applications.

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