Cortina turns to 28-nm for new EDC PHY architecture

Cortina Systems, Inc. says it is the first PHY semiconductor vendor to announce an electronic dispersion compensation (EDC) PHY using 28-nm processes. Thanks to the move to a 28-nm EDC PHY architecture, the new CS4343 Octal 15G EDC device offers latency of less than 1 nsec and a power saving of 50% over previous generations in a 17x17-mm package.

Cortina Systems, Inc. says it is the first PHY semiconductor vendor to announce an electronic dispersion compensation (EDC) PHY using 28-nm processes. Thanks to the move to a 28-nm EDC PHY architecture, the new CS4343 Octal 15G EDC device offers latency of less than 1 nsec and a power saving of 50% over previous generations in a 17x17-mm package.

The CS4343 is designed to meet a wide range of high-density, high-speed requirements, including Gigabit Ethernet (GbE), 10GbE, 40GbE, 100GbE, InfiniBand, Fibre Channel, CPRI, and OBSAI. The fact that it offers EDC on both the ingress and egress pathways also enables KR/KR4 to SFP+/CR4 translation for blade server applications. An integrated 2x2 switch enables support of 1+1 protection switching and broadcast applications. The CS4343 supports link quality monitoring of the inactive redundant link to enable fast switching. According to Scott Feller, director at Cortina Systems, the fact that the device integrates AC coupling capacitors also provides differentiation by significantly simplifying board layout.

The device is fully autonomous, which obviates the need for external processors to control the convergence or dynamic adaption of the dispersion compensation The IC also includes real-time eye monitoring, loopbacks, PRBS generators and checkers, and hardware interrupt and GPIO pins for test and debug.

The ability to produce devices such as the CS4343 in 28-nm opens the door to support of both current high-speed, high-density applications as well as emerging applications with higher-speed electrical interfaces, Feller says. For current designs based on 10 Gbps per lane, the process enables lower power and higher port density. On the drawing board are devices for 25G lanes and multi-level PAM designs, Feller says.

"Latency, power, density, and cost are the critical differentiators for system vendors developing 10G switches for data center, storage, and financial markets," commented Dale Murray, principal analyst at market research firm LightCounting, via a Cortina press release. "This is driving the need for high port density, low latency and power, and high feature integration in all components that go into these switches."

The CS4343 EDC PHY is currently sampling.

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