ClariPhy to demo all-digital EDC transceiver based on MLSD technology at OFC/NFOEC

March 23, 2007
MARCH 23, 2007 -- ClariPhy says it will showcase an all-digital CMOS IC comprising a 10-gigasample/sec analog-to-digital converter and a Maximum Likelihood Sequence Detection electronic dispersion compensation engine.

MARCH 23, 2007 -- ClariPhy Communications Inc. (search for ClariPhy Communications) will demonstrate its 10GBASE-LRM (search for 10GBASE-LRM) integrated circuits (ICs) at next week's OFC/NFOEC Conference in Anaheim, CA.

ClariPhy says it will showcase an all-digital CMOS IC comprising a 10-gigasample/sec analog-to-digital converter (ADC) and a Maximum Likelihood Sequence Detection (search for ) electronic dispersion compensation (search for EDC) engine. The demonstration will include industry-defined, worst-case 300-meter fibers and low-cost SFP+ (search for SFP+) optical modules from such vendors as ExceLight Communications and Picolight.

A digital MLSD architecture has been proven to enable optimal receiver performance for bandwidth-constrained media such as legacy multimode fiber in enterprise backbones, say ClariPhy representatives. Because of the complexities of IC design at rates of 10 Gbits/sec, EDC technology for this application has until now been implemented with sub-optimal analog equalization techniques. Analog equalization suffers from fundamental limitations inherent in analog signal processing, including process-dependence of device parameters, noise sensitivity, and implementation non-idealities, explains the company.

In response to the demand for a better performing product, ClariPhy claims it has developed an all-digital CMOS IC that integrates a low power 10-gigasample/sec ADC and MLSD engine. According to the company, the all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit, say ClariPhy representatives.

"Our engineering team has delivered breakthrough technology that few believed possible," notes Dr. Paul Voois, founder and CEO of ClariPhy. "In developing the first MLSD transceiver for 10GBASE-LRM applications, we have extended the state of the art in numerous areas of IC architecture, VLSI implementation, and mixed-signal design and layout. In addition, history has shown that an all-digital CMOS approach outperforms analog alternatives for challenging communications applications," he adds. "ClariPhy is proud to be the leader in the transition of EDC technology to all-digital architectures, and we are confident that our technology will significantly raise industry standards of performance for 10GBASE-LRM and SFP+ applications."

ClariPhy will demonstrate its MLSD and enabling ADC technology in a private suite at the OFC/NFOEC conference in Anaheim, CA, on March 25-29, 2007. The demonstration will include 10GBASE-LRM data transmission over worst-case 300-meter fibers and SFP+ modules.


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