LogicVision releases newly enhanced embedded SerDes test product
AUGUST 27, 2007 -- LogicVision Inc., a provider of test and yield learning capabilities for the semiconductor industry, today announced major enhancements to its industry-leading embedded SerDes test solution to help customers cope with the cost and challenges of testing multichannel, high-speed, serial I/Os. The new release provides more accurate measurements and the ability to perform bit-error-rate testing (BERT; search for BERT).
High-speed data serialization/deserialization I/O technologies, typically known as SerDes, are being rapidly adopted in data storage, telecommunications, and personal computer applications because they offer reliable, low-power, high data-bandwidth capability using low-cost backplane and connector technologies. Significant test challenges have emerged as multiple SerDes transceivers, with data rates of up to 10 Gbits/sec, are being integrated into systems-on-chip (SoCs). As a result, IC manufacturers are finding it increasingly expensive and time-consuming to guarantee the critical signal-integrity parameters of these high speed I/Os, especially while ramping up yield.
LogicVision says its Embedded SerDes Test product, ETSerdes, is the industry's only vendor-independent, RTL-synthesizable parametric built-in self-test (BIST) for multigigahertz SerDes I/Os. It provides unique capabilities for testing ICs with any number of high-speed serial data channels operating at any frequency, from less than 1 Gbit/sec to more than 10 Gbits/sec. ETSerdes provides test accuracy comparable to that of high-performance external equipment at a fraction of the cost and is compatible with any ATE platform. The ability of the test system to diagnostically measure wave shape, jitter, and jitter tolerance parameters -- each in millisecond test times -- can reduce test costs and improve quality. All of its capabilities can be re-applied at system level to quickly characterize entire signal paths.
The previous release of ETSerdes IP rejected asynchronous noise from its delay measurements by averaging out the noise; the latest release is enhanced to also reject synchronous noise (which cannot be reduced by averaging). This enhancement ensures that the many clock-related noise sources on-chip, especially from pin signals switching at or below the data's parallel rate, have minimal impact on the picosecond delay measurement accuracy.
Additionally, the test device now includes an industry-standard BERT that can be controlled and monitored via a JTAG port or on-chip system signals. The BERT generates and receives a standard 7-bit-based, pseudorandom bit sequence (PRBS7), or a customer-chosen PRBS, to functionally corroborate and extend the existing sub-picosecond resolution jitter and jitter tolerance tests. This embedded capability provides a typically mandatory system-level function, with system and test bus access, and includes automated test generation for quantifying signal path BER.
"As the industry adopts multilane, higher-speed serial I/Os, there's a need for cost-effective test strategies that scale with device performance and complexities," says Farhad Hayat, vice president of marketing at LogicVision. "The latest enhancements to ETSerdes accommodate the increasing levels and types of noise on today's nanometer ICs and deliver more test capabilities for reuse in the end-application."
ETSerdes version 6.0a is in full production and available immediately.
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