Microsemi Corp.(NASDAQ: MSCC) says it has begun shipping engineering samples (ES) of its PolarFire field programmable gate arrays (FPGAs). The devices target such applications as wireline access networks, cellular infrastructure, defense and commercial aviation, as well as such "industry 4.0" spaces as industrial automation and Internet of Things (IoT). The company also now offers a PolarFire Evaluation Kit, which it has already delivered to "key customers." Microsemi says it also has updated its Libero SoC PolarFire Design Suite.
The PolarFire FPGAs feature 12.7G transceivers and come in configurations that support 100K logic elements (LEs) to 500K LEs. The FPGAs require up to 50% less power than competing FPGAs, the company asserts. Microsemi has made ready several demo reference designs, with full design files for Libero SoC PolarFire targeting the PolarFire Evaluation Kit. These include JESD204B Interface, PCI Express (PCIe) Endpoint, 10GBASE-R Ethernet Loopback, DSP FIR Filter, and Multi-Rate Transceiver Demo. The company plans to release additional reference designs over the coming months.
The PolarFire Evaluation Kit, meanwhile, can be used in the context of high-speed transceiver evaluation, 10 Gigabit Ethernet, IEEE 1588, JESD204B, Synchronous Ethernet (SyncE), and CPRI. The kit features a high-pin-count FPGA mezzanine card (FMC), several surface mount assemblies (SMAs), PCIe, dual Gigabit Ethernet RJ45, small form-factor pluggable (SFP) modules, DDR4, and USB.
"After successfully shipping initial ES devices and hardware kits in February to our early access and select Tier 1 customers for system integration and advanced evaluation, we are pleased to reach another key milestone in the PolarFire family rollout by making ES and a high-performance evaluation platform available to our broader customer base," said Shakeel Peera, senior director of SoC product marketing at Microsemi. "The release of the evaluation kit allows customers to port complex designs and test out advanced features—including 12-Gbps package protocols, high-speed DDR3/4 memory interfaces, and general purpose input/outputs (IOs)—as well as complex signal and waveform processing, all in the industry's lowest power, cost-optimized midrange FPGA."
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