The Optical Internetworking Forum (OIF) launched the CEI-112G-XSR project for die-to-die (D2D) and die-to-optical engine (D2OE) Common Electrical Interfaceat its second quarter meeting in April, held in Nuremberg, Germany. The project is intended to enable intra-package interconnects to optical engines, or between dies, with high throughput density and low normalized power with a reach up to 50 mm.
The existing CEI-112G-MCM OIF project is intended for wide, high-bandwidth CMOS-to-CMOS interconnects. OIF says that the new CEI-112G-XSR project also aims to support a mix of technology, specifically the CMOS-to-SiGe often used to build optical engines. System-in-package (SIP) designs lead to a requirement to support as much as 50-mm trace length between the multiple chips on an organic package substrate.
The group says the CEI-112G-XSR project will enable lower normalized power, double shoreline throughput density, and provide a multi-source 72-Gbps to 116-Gbps D2D and D2OE electrical I/O interface. This will progress integration, normalized power reduction, and cost reduction for integrated OE, multiple-die SIPs. The project will also enable 1 to N lanes of 72-Gbps to 116-Gbps electrical I/Os, such as on ASIC/FPGA/OE.
"We jointly designed this project to address the problem of integrating multiple dies, including driver devices for optical engines on non-CMOS technologies, onto a common substrate within a large multi-chip-package design," said Klaus-Holger Otto of Nokia and OIF technical committee chair. "Supporting this mix of technology allows combining the high logic density of CMOS devices with the high drive strength of analog components."
In November of 2017, OIF began work on long reach (LR) and medium reach (MR) CEI-112G projects to build on two existing 100-Gbps serial electrical link projects (see "OIF CEI-112G Project tackles 100-Gbps serial electrical links"). OIF said the CEI-112G-LR project would advance direct attach copper (DAC) cable channel links at 112 Gbps, and the CEI-112G-MR project would progress specifications for a chip-to-chip interface that can also be used to support applications of 112G x 2 (see "OIF CEI-112G Project builds on existing 100-Gbps serial electrical links").
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