Integrated optical transceiver consumes 50% less power
July 28, 2005 Cyberjaya, Malaysia -- SiRES Labs has introduced a version of its integrated transceiver chip which the company says consumes 50% less power than competitive devices. The company says its SRL3101NST optical PMD chip integrates a transimpedance amplifier (TIA), limiting amplifier, VCSEL driver, digital diagnostics (control and status), and LVDS interface.
July 28, 2005 Cyberjaya, Malaysia -- SiRES Labs, a designer of high-speed optical microchips, has introduced a version of its integrated transceiver chip which the company says consumes 50% less power than competitive devices. According to the company, its SRL3101NST optical PMD chip integrates the transimpedance amplifier (TIA), limiting amplifier, VCSEL driver, digital diagnostics (control and status), and LVDS interface, all of which are typically available as individual components.
The transceiver chip is optimized for speeds ranging from 1 Gbit/sec to 3.125 Gbit/sec, and consumes 210 mW of power. The company says the device's low power capability is a result of its integrated functionality. According to the company, with a conventional architecture, all of the device's functions could require as many as three chips, with their respective power consumption. The company notes that conventional architectures result in decreased efficiency due to high power consumption.
The company says the device is designed for use with VCSELs and PIN/APDs in VSR applications including Gigabit Ethernet, SONET VSR links, intra-system, backplanes, SAN, Fibre Channel, and terabit routers and switches. The company says the integrated chip enables smaller form factors without compromising signal quality, while reducing manufacturing costs and component counts in the development of VSR modules and systems.
According to the company, the device's main features include: single +3.3 V operation; peak-to-peak jitter of 20 ps (PRBS23); modulation and bias currents of up to 10 mA, each controllable via an external analog voltage or digitally through the internal registers via a standard, 2-wire serial interface; an integrated temperature sensor; internal closed loop feedback for temperature compensation without the need for an external monitor photodiode; an adjustable VCSEL diode monitor comparator window; tolerance of photodiode input capacitances of up to 1 pF; input current ranging from 15 µA to 800 µA; a programmable threshold for low input signal detect feature and an average input current monitor output. The device's digital status signals are accessible via internal registers or through the serial digital interface.
The SRL3101NST is available as a bare die with large bond pad pitches. Using the CMOS process, the chip is designed using proprietary dynamic self-adaptive biasing (dSAB) technology, which the company says compensates for process and temperature induced parametric variations, and allows for a higher yield of analog circuits in the CMOS process.
The device and an evaluation board are available for sampling.