Link-evaluation system

March 1, 1995

Link-evaluation system

The evaluation system provides control, stimulus and evaluation functions to analyze high-speed data communications links using the VSC7105/7106/7107 chipset at 1.0625 Gbits/sec. The VSC7105 transmitter and VSC7106 receiver incorporate mixed-signal circuitry with a phase-locked loop for clock multiplication and recovery. The VSC7107 encoder/decoder implements the FC-1 layer of the Fibre Channel protocol, including 8B/10B encode/decode, cyclic redundancy check generation and link-management functions. The evaluation system consists of an exerciser board, a system interface board containing the encoder/decoder and a physical layer transceiver module containing the transmitter and receiver.

Vitesse Semiconductor Corp.

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