The TQ8105 Sonet/SDH transceiver handles an STS-12/STM-4 or STS-3/STM-1 rate by integrating multiplexing, demultiplexing, Sonet/SDH framing, clock synthesis phase-locked loop, and line and clock diagnostic functions into a monolithic device. It features direct connection with either positive emitter coupled logic or emitter coupled logic high-speed input/output circuits, allowing selection of external clock and data recovery, optoelectronic module and reference clock sources. The on-chip phase-locked loop uses an external reference-clock-based loop filter and supports the range of reference-clock frequencies found in Sonet/SDH/STM systems. For transmit clock synthesis, the phase-locked loop exceeds ANSI, Bellcore and ITU jitter specifications for systems when combined with industry typical optoelectronic devices. It also provides byte clocks and constant rate 38.88- and 51.84-MH¥synthesized clock outputs. Operating from a 5V supply, the transceiver provides direct connected positive emitter coupled logic levels for high-speed input/output, direct connection to high-speed input/output using emitter coupled logic levels with a -5V supply, low-speed bus, control and clock input/output TTL, or transistor-transistor-logic, levels. It comes in a 100-pin 14䂂-mm JEDEC plastic package and operates at -40 to +125C.
Triquint Semiconductor Inc.