Cortina and Xilinx connect at 40G using Interlaken

JANUARY 24, 2007 -- Cortina Systems (search for Cortina Systems) and Xilinx Inc. (search for Xilinx) today announced successful interoperability of the Virtex-5 FPGA and Cortina's new CS3477 Ethernet MAC aggregation IC, via the Interlaken (search for Interlaken) protocol. Interlaken, an open specification for high-speed chip-to-chip packet transfers using the latest serial technology, enables component manufactures to scale their devices to 40 Gbits/sec and beyond.

"Designers need maximum interconnect performance, and our customers have been asking for technologies like Interlaken to break the bandwidth ceiling imposed by SPI.4," explains Per Holmberg, director of programmable digital systems at Xilinx. "Interlaken leverages the Virtex-5 advanced serial transceiver technology, providing 40 Gbits today with a runway up to 100 Gbits or more. With Sarance Technologies previous announcement of their IP for our Virtex-5 family, a completely verified solution is available now," he reports.

"This announcement further demonstrates Interlaken's ability to eliminate bandwidth restrictions and increase performance for communications applications that require the highest possible performance," adds Fred Olsson, product manager at Cortina Systems. "We have seen an outpouring of industry support for Interlaken since its launch just a few months ago, and we are very pleased to welcome Xilinx as a member in the Interlaken ecosystem."

This demonstration connected the data from four wire-speed 10-Gigabit Ethernet ports across a Xilinx FPGA and a Cortina CS3477 device.

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